Based on the gm/Id lookup table methodology, a residue amplifier for a 14-bit 100 MS/s pipelined successive approximation register analog-to-digital converter (Pipelined-SAR ADC) was designed. The residue amplifier used a high-gain and wide-bandwidth gain-boosted operational amplifier (OTA) structure. The methodology used a lookup function to find the DC operating point of the devices, which overcame the problem that the conventional method could not accurately design the parameters of the short channel devices. Through the iterative algorithm to select the gm/Id of the core devices, the circuit could achieve optimal design of power consumption while meeting the performance requirements, and had a nice process portability. The OTA performance of the design was simulated and verified in SMIC 55 nm CMOS process. The optimized design of the circuit power consumption of 1.9 mW under the multi-dimensional constraints such as a DC gain of 92 dB, a closed-loop -3 dB bandwidth of 180 MHz and a noise (rms) of 1.44 mV was realized.