Fig. 1. (Color online) (a) The schematic diagram of the typical FeRAM 1T−1C array, in which the transistors are controlled by WLs and the ferroelectric capacitors are controlled by PLs and BLs. (b) The readout circuit of the FeRAM 1T−1C bit-cell. (c) Timing diagrams for the read operation scheme of the 1T1C FeRAM cell for data "0" and data "1". Misreading occurs at high temperature (100 ℃).

Fig. 2. (Color online) (a) and (b) The sensing current and corresponding charge for bits "1" during read operations at 25 and 100 ℃. (c) For FE devices, pronounced reduction in switching polarization signal reading at elevated temperature is observed. The sense margin may decrease when operating at high temperature (100 ℃).

Fig. 3. (Color online) (a) The TEM image of the TiN/HZO/TiN capacitor. (b) The fabrication process of FE devices.

Fig. 4. (Color online) High temperature imprint test at 200 ℃ for TiN/HZO/TiN capacitors. (a) The corresponding P−V loops for HZO devices after different baking time from 0−10 000 min. (b) Evolution of extracted ∆E_c vs baking time.

Fig. 5. (Color online) (a) Schematic diagram of hysteresis loop of a FE capacitor caused by imprint. (b) Baking testing scheme for ferroelectric devices with different operating voltages. (c) and (d) Comparison of switching polarization of ferroelectric capacitors before and after baking. The pronounced degradation of the FeRAM memory is observed for low operation voltage devices in high temperature.

Fig. 6. (Color online) Evolution of remanent polarization with electric field cycling using rectangular pulses. The HZO FE capacitors exhibit three states: Less waked-up, waked-up and fatigue. (b) Imprint test flow for three samples.

Fig. 7. (Color online) (a) ∆E_c as a function of baking time with different number of cycles before bake when the FE device is fatigued, the degree of imprint was worse. (b)−(d) P−V hysteresis loops of the MFM capacitor with 10 nm HZO film before and after high-temperature annealing. (e)−(h) The corresponding FORCs measurements after 1000 min at 150 ℃ annealing for three cases.

Fig. 8. (Color online) The proposed sensing circuit to overcome the misreading problem. (a) and (b) Schematics of the solution and the circuit. (c) The working temperature of the selected Bank 1 changes from 25 to 85 ℃ and the write voltage then changes from 2 to 3.5 V.