• Chip
  • Vol. 3, Issue 3, 100098 (2024)
Wentao Qian, Junzhuan Wang*, Jun Xu, and Linwei Yu**
Author Affiliations
  • School of Electronic Science and Engineering/National Laboratory of Solid-State Microstructures, Nanjing University, Nanjing 210093, China
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    DOI: 10.1016/j.chip.2024.100098 Cite this Article
    Wentao Qian, Junzhuan Wang, Jun Xu, Linwei Yu. Channel-bias-controlled reconfigurable silicon nanowire transistors via an asymmetric electrode contact strategy[J]. Chip, 2024, 3(3): 100098 Copy Citation Text show less
    References

    [1] F. Wanlass, C. Sah. Nanowatt logic using field-effect metal-oxide semiconductor triodes.

    [2] T. Ghani, et al..

    [3] D. Wang, B.A. Sheriff, J.R. Heath. Complementary symmetry silicon nanowire logic: power-efficient inverters with gain. Small, 2 (2006), pp. 1153-1158.

    [4] S.C. Rustagi, et al.. CMOS inverter based on gate-all-around silicon-nanowire MOSFETs fabricated using top-down approach. IEEE Electron Device Lett., 28 (2007), pp. 1021-1024.

    [5] N.H. Van, et al.. High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage. Nanoscale, 6 (2014), pp. 5479-5483.

    [6] H.C. Lin, K.L. Yeh, R.G. Huang, C.Y. Lin, T.Y. Huang. Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain extension. IEEE Electron Device Lett., 22 (2001), pp. 179-181.

    [7] D. Zhang, T. Chow, M. Wong. A polycrystalline silicon thin-film transistor with self-aligned metal electrodes formed using aluminum-induced crystallization. IEEE Trans. Electron Devices, 55 (2008), pp. 2181-2186.

    [8] F. Wessely, T. Krauss, U. Schwalke. CMOS without doping: multi-gate silicon-nanowire field-effect-transistors. Solid-State Electron, 70 (2012), pp. 33-38.

    [9] A. Heinzig, T. Mikolajick, J. Trommer, D. Grimm, W.M. Weber. Dually active silicon nanowire transistors and circuits with equal electron and hole transport. Nano Lett., 13 (2013), pp. 4176-4181.

    [10] J. Zhang, X.F. Tang, P.-E. Gaillardon, G. De Micheli. Configurable circuits featuring dual-threshold-voltage design with three-independent-gate silicon nanowire FETs. IEEE Trans. Circuits Syst. I: Regul. Pap., 61 (2014), pp. 2851-2861.

    [11] L. Wind, et al.. Nanoscale reconfigurable Si transistors: from wires to sheets and unto multi-wire channels. Adv. Electron. Mater., 10 (2024), p. 2300483.

    [12] M. Simon, et al.. Top-down fabricated reconfigurable FET with two symmetric and high-current on-states. IEEE Electron Device Lett., 41 (2020), pp. 1110-1113.

    [13] X. Yang, K. Mohanram. Modeling and performance investigation of the double-gate carbon nanotube transistor. IEEE Electron Device Lett., 32 (2011), pp. 231-233.

    [14] G.T. Lu, et al.. Reconfigurable tunneling transistors heterostructured by an individual carbon nanotube and MoS2. Nano Lett., 21 (2021), pp. 6843-6850.

    [15] Y.-M. Chang, et al.. Reversible and precisely controllable p/n-Type doping of MoTe2 transistors through electrothermal doping. Adv. Mater., 30 (2018), p. 1706995.

    [16] X. Sun, et al.. Reconfigurable logic-in-memory architectures based on a two-dimensional van der Waals heterostructure device. Nat. Electron., 5 (2022), pp. 752-760.

    [17] R. Peng, et al.. Programmable graded doping for reconfigurable molybdenum ditelluride devices. Nat. Electron., 6 (2023), pp. 852-861.

    [18] J.J. Rodriguez-Andina, M.J. Moure, M.D. Valdes. Features, design tools, and application domains of FPGAs. IEEE Trans. Ind. Electron., 54 (2007), pp. 1810-1823.

    [19] S. Rai, et al.. Designing efficient circuits based on runtime-reconfigurable field-effect transistors. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 27 (2019), pp. 560-572.

    [20] J.-H. Bae, et al.. Reconfigurable field-effect transistor as a synaptic device for XNOR binary neural network. IEEE Electron Device Lett., 40 (2019), pp. 624-627.

    [21] C. Pan, et al.. Reconfigurable logic and neuromorphic circuits based on electrically tunable two-dimensional homojunctions. Nat. Electron., 3 (2020), pp. 383-390.

    [22] A. Heinzig, S. Slesazeck, F. Kreupl, T. Mikolajick, W.M. Weber. Reconfigurable silicon nanowire transistors. Nano Lett., 12 (2011), pp. 119-124.

    [23] M. Mongillo, P. Spathis, G. Katsaros, P. Gentile, S. De Franceschi. Multifunctional devices and logic gates with undoped silicon nanowires. Nano Lett., 12 (2012), pp. 3074-3079.

    [24] S.J. Park, et al.. Reconfigurable Si nanowire nonvolatile transistors. Adv. Electron. Mater., 4 (2018), p. 1700399.

    [25] D.-Y. Jeon, S.J. Park, S. Pregl, T. Mikolajick, W.M. Weber. Reconfigurable thin-film transistors based on a parallel array of Si-nanowires. J. Appl. Phys., 129 (2021), p. 124504.

    [26] Y. Cui, Z. Zhong, D. Wang, W.U. Wang, C.M. Lieber. High performance silicon nanowire field effect transistors. Nano Lett., 3 (2003), pp. 149-152.

    [27] W.M. Weber, et al.. Silicon nanowires: catalytic growth and electrical characterization. Phys. Status Solidi (B), 243 (2006), pp. 3340-3345.

    [28] W.S. Wong, S. Raychaudhuri, R. Lujan, S. Sambandan, R.A. Street. Hybrid Si nanowire/amorphous silicon FETs for large-area image sensor arrays. Nano Lett., 11 (2011), pp. 2214-2218.

    [29] L.W. Yu, P.-J. Alet, G. Picardi, P.R.I. Cabarrocas. An in-plane solid-liquid-solid growth mode for self-avoiding lateral silicon nanowires. Phys. Rev. Lett., 102 (2009), p. 125501.

    [30] L. Yu, P.R.I. Cabarrocas. Initial nucleation and growth of in-plane solid-liquid-solid silicon nanowires catalyzed by indium. Phys. Rev. B, 80 (2009), Article 085313.

    [31] L. Yu, M. Oudwan, O. Moustapha, F. Fortuna, P.R.I. Cabarrocas. Guided growth of in-plane silicon nanowires. Appl. Phys. Lett., 95 (2009), p. 113106.

    [32] L. Yu, et al.. Growth-in-place deployment of in-plane silicon nanowires. Appl. Phys. Lett., 99 (2011), p. 203104.

    [33] L. Yu, P.R.I. Cabarrocas. Growth mechanism and dynamics of in-plane solid-liquid-solid silicon nanowires. Phys. Rev. B, 81 (2010), Article 085323.

    [34] L. Yu, P.R.I. Cabarrocas. Morphology control and growth dynamics of in-plane solid-liquid-solid silicon nanowires. Phys. E: Low-Dimens. Syst. Nanostructures, 44 (2012), pp. 1045-1049.

    [35] J. Zhang, P.-E. Gaillardon, G. De Micheli. Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE (2013), pp. 2111-2114.

    [36] J. Zhang, M. De Marchi, P.E. Gaillardon, G.A. De Micheli. Schottky-barrier silicon FinFET with 6.0 mV/dec subthreshold slope over 5 decades of current. 2014 IEEE International Electron Devices Meeting, IEEE (2014), pp. 13.4.1-13.4.4.

    [37] R. Hu, et al.. Unprecedented uniform 3D growth integration of 10-layer stacked Si nanowires on tightly confined sidewall grooves. Nano Lett., 20 (2020), pp. 7489-7497.

    [38] R. Hu, et al.. Ultra-confined catalytic growth integration of sub-10 nm 3D stacked silicon nanowires via a self-delimited droplet formation strategy. Small, 18 (2022), p. 2204390.

    [39] W. Qian, et al.. Converging-guiding-track design enables 100% growth deployment rate of ultrathin monocrystalline silicon nanowire channels. Appl. Phys. Lett., 122 (2023), p. 173101.

    [40] M. Xu, et al.. Operating principles of in-plane silicon nanowires at simple step-edges. Nanoscale, 7 (2015), pp. 5197-5202.

    [41] M. Xu, et al.. High performance transparent in-plane silicon nanowire Fin-TFTs via a robust nano-droplet-scanning crystallization dynamics. Nanoscale, 9 (2017), pp. 10350-10357.

    [42] Z. Xue, et al.. Deterministic line-shape programming of silicon nanowires for extremely stretchable springs and electronics. Nano Lett., 17 (2017), pp. 7638-7646.

    [43] X. Wu, et al.. 3D sidewall integration of ultrahigh-density silicon nanowires for stacked channel electronics. Adv. Electron. Mater., 5 (2019), p. 1800627.

    [44] W. Chen, et al.. Incorporation and redistribution of impurities into silicon nanowires during metal-particle-assisted growth. Nat. Commun., 5 (2014), p. 4134.

    [45] Y. Sun, et al.. Unexpected phosphorus doping routine of planar silicon nanowires for integrating CMOS logics. Nanoscale, 13 (2021), pp. 15031-15037.

    [46] L.L. Xu, J. Wang, H.S. Liu, Z.P. Jin. Thermodynamic assessment of the Pt-Si binary system. Calphad, 32 (2008), pp. 101-105.

    [47] S. Roy, S.V. Divinski, A. Paul. Reactive diffusion in the Ti–Si system and the significance of the parabolic growth constant. Philos. Mag., 94 (2013), pp. 683-699.

    Wentao Qian, Junzhuan Wang, Jun Xu, Linwei Yu. Channel-bias-controlled reconfigurable silicon nanowire transistors via an asymmetric electrode contact strategy[J]. Chip, 2024, 3(3): 100098
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