A programmable high speed and wideband frequency divider was designed and implemented in a 0.18 μm SiGe BiCMOS process. The methods for optimizing high and wideband frequency was analyzed for the divider. A /4/5 or /8/9 prescaler with switchable module value and a M/A counter based on CML difference structure were proposed, which achieved a wideband working frequency. The measurement results showed that the operating frequency of the divider could cover 1~10 GHz, and the RF input sensitivity of the whole band was lower than -10 dBm.