[2] CHEN S H, LINTEN D, LEE J W, et al. Gated and STI defined ESD diodes in advanced bulk FinFET technologies [C] // IEEE International Electron Devices Meeting (IEDM). San Francisco, CA, USA. 2014: 20.4.1-20.4.4.
[3] GRIFFONI A, THIJS S, RUSS C, et al. Next generation bulk FinFET devices and their benefits for ESD robustness [C] // 31th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD). Anaheim, CA, USA. 2009: 1-10.
[4] LINTEN D, HELLINGS G, CHEN S H, et al. ESD performance of high mobility SiGe quantum well bulk finFET diodes and PMOS devices [C] // 35th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD). Las Vegas, NV, USA. 2013: 1-8.
[5] LEE J H, PRABHU M, KORABLEV K, et al. Methodology to achieve planar technology-like ESD performance in FINFET process [C] // IEEE International Reliability Physics Symposium (IRPS). Monterey, CA, USA. 2015: 3F.3.1-3F.3.6.
[6] LI Y, MIAO M, GAUTHIER R. Design and optimization of ESD P-direction diode in bulk FinFET technology [C] // 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD). Reno, NV, USA. 2018: 1-7.
[7] KUMAR B S, PAUL M, GOSSNER H, et al. Physical insights into the ESD behavior of drain extended FinFETs [C] // 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD). Reno, NV, USA. 2018: 1-7.
[8] PAUL M, KUMAR B S, NAGOTHU K K, et al. Drain-extended FinFET with embedded SCR (DeFinFET-SCR) for high-voltage ESD protection and self-protected design [J]. IEEE Transactions on Electron Devices, 2019, 66(12): 5072-5079
[9] MONISHMURALI M, SHRIVASTAVA M. A novel high voltage drain extended FinFET SCR for SoC applications [C] // IEEE International Reliability Physics Symposium (IRPS). Monterey, CA, USA. 2021: 1-4.
[10] WANG A . On-chip ESD protection for integrated circuits: an IC design perspective [M]. New York: Springer US, 2002: 59-70.