【AIGC One Sentence Reading】:This paper analyzes short-circuit failures in 1.2 kV SiC MOSFETs, revealing distinct mechanisms at 400V and 800V, and proposes robustness enhancement strategies.
【AIGC Short Abstract】:This paper investigates short-circuit failure mechanisms in 1.2 kV planar SiC MOSFETs, comparing two products under 400 and 800 V conditions. Cracking due to differential thermal expansion at 400 V and gate oxide degradation at 800 V are identified as key failure mechanisms. Strategies to enhance SiC MOSFET robustness against these failures are proposed.
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Abstract
This paper presents a comprehensive analysis of the short-circuit failure mechanisms in commercial 1.2 kV planar silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) under 400 and 800 V bus voltage conditions. The study compares two products with varying short-circuit tolerances, scrutinizing their external characteristics and intrinsic factors that influence their short-circuit endurance. Experimental and numerical analyses reveal that at 400 V, the differential thermal expansion between the source metal and the dielectric leads to cracking, which in turn facilitates the infiltration of liquid metal and results in a gate–source short circuit. At 800 V, the failure mechanism is markedly different, attributed to the thermal carrier effect leading to the degradation of the gate oxide, which impedes the device's capacity to switch off, thereby triggering thermal runaway. The paper proposes strategies to augment the short-circuit robustness of SiC MOSFETs at both voltage levels, with the objective of fortifying the device's resistance to such failures.
1. Introduction
Third-generation semiconductor materials, such as silicon carbide (SiC), are noted for their exceptional properties, including a wide band-gap, high breakdown field, and high electron mobility, among others. These attributes are paramount for improving efficiency of electric energy utilization[1]. Nowadays, SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) have reached a commercial maturity and are widely used in various power conversion circuits as well as new energy vehicles[2].
During the operation of a power converter, a high DC voltage is required to be applied to the SiC MOSFETs drain in the off state. However, certain faults may cause the high DC voltage to being directly applied to the SiC MOSFETs in the on state, leading the device to operate in a shorted condition. Therefore, it is necessary for the power device to be able to withstand a short-circuit fault for a minimum of 10 μs before the short-circuit protection circuit is activated[3]. However, the short-circuit capability is not a concern for Si devices, it poses a challenge for SiC MOSFETs. Due to their smaller chip sizes and higher current densities, SiC MOSFETs tend to have shorter short-circuit withstand times compared to traditional Si-based devices[4, 5].
In recent years, considerable research has been dedicated to the short-circuit reliability of SiC MOSFETs. Literature suggests that device degradation typically occurs following a short-circuit current pulse of approximately 30 μs, with a DC voltage of 400 V, gate voltage of 18 V, and within a temperature range of 90 to 150 °C. Additionally, a trailing current was observed prior to device degradation[6]. Some studies have indicated that the short-circuit capability of SiC MOSFETs is weaker compared to Si insulated gate bipolar transistor (IGBT). For instance, a 1200 V Si IGBT can endure a short-circuit time of 33 μs, whereas a 1200 V SiC MOSFET can only manage a short-circuit time of 8 μs[7, 8]. The SiC MOSFETs available on the market currently feature a planar structure, and their capacity to withstand short-circuits, in terms of both time and energy, decreases as the DC voltage increases to 400, 500, and 600 V[9]. Researchers have further probed the degradation mechanism of both static and dynamic characteristics in 1200 V SiC MOSFETs through rigorous repeated short-circuit testing[10, 11]. Nevertheless, there remains an urgent requirement for more extensive research into the failure modes and intrinsic failure mechanisms of SiC MOSFETs subjected to short-circuited. These aspects are of utmost importance in enhancing device short-circuit tolerance and overall reliability.
This paper concentrates on the short-circuit characteristics of planar SiC MOSFETs with a rated voltage of 1.2 kV, carrying out a meticulous study under DC voltages of 400 and 800 V. By merging theoretical knowledge with empirical data, it uncovers novel mechanisms of short-circuit failure.
2. Short-circuit characteristic
2.1. Short-circuit test results at 400 V bias DC voltage
The short-circuit characteristics of two 1.2 kV class planar SiC MOSFETs (Product A: rated current 36 A; Product B: rated current 32 A) were selected for hard-switching fault short circuit testing. Fig. 1 illustrates the single-pulse short-circuit test bench under hard-switching fault, comprising the schematic diagram and physical diagram. UDC represents the DC bias voltage supplied by the DC power source, CB denotes the circuit breaker, Rg stands for the gate drive resistor, and UG signifies the single-pulse drive signal. Furthermore, Cgs, Cgd, and Cds denote the parasitic capacitance of the SiC MOSFETs, while Lg, Ld, and Ls represent the parasitic inductance of the gate, drain, and source, respectively. These inductance encompass both the external leads and internal connections of the device.
Figure 1.(Color online) Single pulse short-circuit test bench. (a) Schematic diagram and (b) physical diagram.
The gate–source junction experienced a short-circuit failure under the following test conditions: a bus DC voltage of 400 V, gate drive voltage ranging from +15 to −5 V, and a gate drive resistance of 5 Ω. Each pulse interval lasted 2 min to mitigate the impact of temperature rise on the device. The pulse width was gradually increased from 1 μs by 0.5 μs until device failure occurred.
Fig. 2 (a) illustrates the short-circuit waveform of the Product A during hard-switching failure at a bias voltage of 400 V. In the initial stages, the device temperature remained low, with ionized impurity scattering being dominant. As temperature increased, carrier mobility rose, resulting in a peak drain current of 310 A. However, as temperature continued to rise, lattice scattering became the predominant factor, causing to a gradual reduction in drain current to 100 A. At a pulse width of 11.5 μs, the device experienced significant current drag, eventually leading to a complete shutdown with a current of 0 A. The gate bias voltage successfully reached −5 V before the gate–source short circuit occurred, with a delay of 3 μs, resulting in VGS of 0 V. Resistance measurements between the device electrodes were conducted using a multimeter, yielding the following results: gate–source resistance (Rgs) = 1.9 Ω, gate–drain resistance (Rgd) = 9.60 MΩ, source–drain resistance (Rsd) = 9.60 MΩ, and drain–source resistance (Rds) = ∞. As a consequence of the gate–source short circuit, the Rgd closely resembled the Rsd.
Figure 2.(Color online) Short-circuit waveform of SiC MOSFETs at 400 V DC voltage. (a) Product A, (b) Product B.
Fig. 2 (b) illustrates the short-circuit failure waveforms at 400 V bus voltage for Product B. As temperature increased, carrier mobility rose, resulting in a peak drain current of 160 A. At a pulse width of 20 μs, the device experienced significant current drag, eventually leading to a complete shutdown with a current of 0 A. The gate bias voltage successfully reached −5 V before the gate–source short circuit occurred, with a delay of 2.25 μs, resulting in VGS of 0 V. It is obvious that the short-circuit withstand time of Product B at 400 V bus voltage is twice as long as that of Product A, owing to the fact that Product B possesses a smaller short-circuit saturation current.
2.2. Short-circuit test results at 800 V bias DC voltage
The thermal runaway failure short-circuit test was carried out with the following parameters: a bus DC voltage of 800 V, a gate drive voltage that varied from +15 to −5 V, and a gate drive resistance of 5 Ω. Each pulse interval was set to last 2 min to alleviate the effects of temperature accumulation on the device. The pulse width was gradually increased from 1 μs, increasing by 0.25 μs with each iteration. The short-circuit waveform of the Product A under a DC bias voltage of 800 V is shown in Fig. 3 (a). At a pulse width of 2.75 μs, the current initially peaked at 290 A, but then it dropped to 170 A as thermal runaway occurred. Regrettably, the device failed to shut down properly, leading to a sudden spike in leakage current and an eventual breakdown, marked by a loud noise. Resistance measurements between the device electrodes were conducted using a multimeter, yielding the following results: Rgs = 1.0 Ω, Rgd = 0.9 Ω, Rsd = 0.9 Ω, and Rds = 1.0 Ω.
Figure 3.(Color online) Short-circuit waveform of SiC MOSFETs at 800 V DC voltage. (a) Product A, (b) Product B.
Fig. 3 (b) depicts the short-circuit failure waveforms at 800 V bus voltage for Product B. At a pulse width of 4.5 μs, the current initially peaked at 200 A, only to subside to 110 A when thermal runaway occurred. Similar to the short-circuit failure at a bus voltage of 400 V, the short-circuit withstand time of Product B is twice as long as that of Product A, owing to the smaller short-circuit saturation current of Product B. As a result, the short-circuit saturation current of SiC MOSFETs exerts a substantial influence on the short-circuit endurance across various bus voltages during short-circuit failures.
3. Post-failure analysis
3.1. Chip surface observation
Given the identical failure characteristics observed in both Product A and Product B, the study will concentrate on examining one of the products to elucidate the underlying mechanisms behind internal short-circuit induced failure. The defective device was subjected to laser uncapping to remove the outer package, thereby exposing the internal structure. Fig. 4 (a) shows the chip surface image of the MOSFETs after a 400 V DC short-circuit test. Despite the gate–source short circuit, no substantial damage was detected on the device’s surface. Nevertheless, Fig. 4 (b), which depicts the chip surface after the 800 V DC short-circuit test, clearly shows that the metal on the device’s surface has melted, signifying irreversible damage. This finding implies that the temperature spike the device was subjected to at the moment of failure was extraordinarily high.
Figure 4.(Color online) Chip surface of post-failure SiC MOSFETs after short circuit. (a) 400 V, (b) 800 V.
Based on the impedance test results detailed in Section Ⅱ, it is apparent that the planar type SiC MOSFETs only suffers a gate–source short-circuit failure subsequent to the 400 V short-circuit test. This suggests the presence of a conductive pathway solely between the gate and the source, where insulation was intended to be maintained. To ascertain the precise location of the short circuit, both the gate–source leakage current (IGSS) and drain–source leakage current (IDSS) of the device were measured using a Keysight B1505A semiconductor analyzer, both prior to and following the device's disassembly. As shown in Fig. 5(a), it is noteworthy that the IGSS measures 1 μA, markedly surpassing the typical threshold of 250 nA. Moreover, as the drain voltage varies from 0 to 100 V, the drain–source leakage current gradually increases from 7 to 100 μA. This empirical data substantiates the existence of a direct conduction path at the gate–source junction, uninfluenced by the package casing.
Figure 5.(Color online) (a) Gate−source leakage current and (b) drain−source leakage current before and after opening the lid.
Once the device had been removed, the leakage current was harnessed to pinpoint the location of the hot spot. With drain voltage (VD) set to 30 V and IDSS measured at 160 μA, the hot spot was detected within the array area. Fig. 6 delineates the localization of the chip’s leakage heat. Following this, a focused ion beam (FIB)-transmission electron microscope (TEM) system was deployed to conduct a cross-section analysis across the hot spot, meticulously sectioning the layers until the conductive path was exposed. Fig. 7 presents the FIB cross-section image of the failure point. The analysis disclosed a crack within the gate inter-layer dielectric, situated between the gate poly-silicon and the source aluminum (Al).
Figure 6.(Color online) Hot spot location. (a) Over all view of chip, (b) zoomed in the hot spot.
The FIB-TEM images were subjected to a meticulous layer-by-layer examination, which revealed no cracks in the gate SiO2 layer of the planar-type SiC MOSFETs. This absence of cracks can be attributed to the significant difference in the thermal expansion coefficients of the gate poly-silicon (2.9 × 10−6 K−1), the gate dielectric layer (0.5 × 10−6 K−1), and the source Al metal (23.2 × 10−6 K−1). The gate dielectric layer is incapable of withstanding the high-temperature thermo-mechanical stresses engendered by the short-circuiting, leading to the deformation of these layers and the eventual cracking of the gate dielectric layer. During short-circuit conditions, the considerable power dissipation triggers a swift rise in the junction temperature of the SiC MOSFETs. Moreover, the infinite impedance of Rgd and Rds confirms the integrity of the gate SiO2 layer and the PN junction. The time lag observed between gate shutdown and the ultimate short-circuit failure in the 400 V short-circuit transient indicates that mechanical stresses necessitate a period to propagate and instigate cracks.
4. Electro-thermal-mechanical simulation
4.1. Modelling of SiC MOSFETs
To delve deeper into the internal dynamics of SiC MOSFETs during short-circuit incidents, the TCAD simulation is employed to replicate the electrical and thermal conditions within the device. The simulation parameters for the SiC MOSFETs are delineated as follows: The thickness of the epitaxial drift layer and doping concentration are set to 13 μm and 9 × 1015 cm−3, respectively. The Pwell region has a doping concentration of 5 × 1013 cm−3, whereas the P+ doping in the implantation base region ranges from 5 × 1017 cm−3 to 5 × 1018 cm−3, as ascertained through ion implantation simulation[12]. The substrate thickness and doping concentration are set to 10 μm and 1 × 1019 cm−3, respectively. The channel length is set at 1 μm, with a doping concentration of 5 × 1015 cm−3, and the P+ doping concentration is also set to 5 × 1015 cm−3.
The top-level structure of the virtual unit cell MOSFETs, constructed in TCAD and informed by TEM images, is depicted in Fig. 8. Acknowledging that the material properties of SiC fluctuate at elevated temperatures, the simulation incorporates coupled electrical and thermal calculations[13]. Physical models, including periodic boundary conditions, the Okuto−Crowell impact ionization model, high-field saturation, temperature-dependent bandgap and mobility, and thermodynamics, are factored into the simulation. The thermal contact resistance at the drain surface is calibrated to 0.034 K·cm2/W for planar MOSFETs, aligning with the thermal resistance delineated in the datasheet. To guarantee accurate temperature outcomes, the bulk specific heat capacities of SiC and Al are fine-tuned in accordance with the data presented in Ref. [14].
Figure 8.(Color online) SiC MOSFET structure schematic diagram.
In the TCAD simulation, a short-circuit test simulation circuit is constructed using the mixed-model system. The parameters are meticulously set as follows: The DC bias voltage is calibrated to 400 V, and the pulse width is adjusted to 11 μs to emulate a genuine short-circuit scenario. This configuration enables the simulation to faithfully replicate the electrical and thermal behavior of the SiC MOSFETs during a short-circuit event.
The short-circuit current waveforms for both the simulation and measurement devices are shown in Fig. 9, with a DC bias voltage of 400 V. It can be observed that the simulation fitting yields satisfactory results. Meanwhile, Fig. 10 illustrates the internal temperature distribution at the point of device shutdown. Upon scrutiny of Fig. 10, it becomes apparent that the elevated temperature is primarily focused in the JFET region proximate to the gate oxide layer, with the maximum temperature reaching 1300 K. Furthermore, temperatures exceeding 1180 K are detected in the Al metal and the source contact regions. Considering that the melting point of Al is roughly 935 K, it strongly indicates that the Al metal is in a liquid state under these conditions.
Figure 9.(Color online) Comparison of short-circuit characteristics between simulated and measured devices at 400 V DC bias voltage.
The presence of a crack between the gate and source, as depicted in Fig. 7, is attributed to the disparate expansion coefficients of the materials involved. As a result, there is a significant likelihood that the liquid Al metal will seep into these fissures, thereby creating a conductive path between the gate and source, which were initially insulated. This phenomenon ultimately manifests as a gate–source short-circuit, leading to device failure. This explains the disparity in short-circuit tolerance intervals between Product A and Product B. Product A, which boasts a higher short-circuit saturation current, generates a greater quantity of heat over an equivalent short-circuit duration, thus hastening the rate of device degradation.
Hence, opting for a metal with a higher melting point and a coefficient of thermal expansion (CTE) more closely aligned with that of the gate dielectric layer is a prudent selection. Platinum (Pt) stands out as an outstanding candidate metal owing to its high melting point and moderate CTE. The high melting point of Pt, approximately 2047 K, implies its resistance to softening or melting in high-temperature environments, thus ensuring device stability. Moreover, its relatively lower CTE, approximately 9.0 × 10−6 K−1 compatibility with the expansion rate of the gate dielectric layer, reducing the effects of thermal stress on the device. Choosing Pt as the source electrode metal or introducing a layer of Pt between the gate dielectric layer and the source electrode metal can significantly enhance device performance and reliability. This design may effectively mitigate the risk of gate–source breakdown, thus prolonging the device's service life and presenting itself as a potential avenue for optimization.
4.3. Short-circuit simulation at 800 V DC bias
Fig. 11 compares the short-circuit current waveforms of simulated devices and measured devices under an 800 V bias voltage. It can be observed that the simulation fitting yields satisfactory results. The conduction of parasitic transistors leading to the generation of a large current is a typical failure mechanism under an 800 V bus voltage[15, 16]. The current experiment has discovered a new failure mechanism: During the short-circuit test, the loss of gate oxide due to the hot carrier effect results in the inability of the gate to turn off properly, causing the current to continuously increase until the device fails.
Figure 11.(Color online) Comparison of short-circuit characteristics between simulated and measured devices at 800 V DC bias voltage.
Fig. 12(a) delineates the distribution of the vertical electric field across the SiC/SiO2 interface channel region and the JFET region, under an 800 V bus voltage. It is particularly striking that during the short-circuit state, the simulated results indicate an anomalously intensified gate oxide electric field within the device. The vertical electric field, derived from the SiC/SiO2 interface, peaked at over 3.29 MV/cm. Fig. 12(b) shows the distribution of the impact ionization rate during the short-circuit process, revealing a substantial creation of electron−hole pairs in proximity to the gate oxide in the JFET region and at the corners of the p-well. Propelled by the augmented vertical electric field across the entire oxide layer, these electron−hole pairs have precipitated a notable hot carrier injection effect. Concurrently, the elevated temperature at the device surface has exacerbated the hot carrier injection effect within the gate oxide.
Figure 12.(Color online) (a) Electrical-field along SiC/SiO2 interface and (b) impact ionization distribution for short-circuit end transient at 800 V DC bias voltage.
However, owing to the abrupt escalation in thermal stress and electric field, the gate oxide situated above the channel has become the most vulnerable component. It is therefore postulated that, under the confluence of thermal stress and electric field, the impingement of hot carriers could induce damage to the gate oxide, thereby hindering the gate's capacity to effectively impede the current from the source to the drain. This culminates in the device's failure to shut down correctly, ultimately precipitating device failure due to an abrupt increase in current.
Based on the principle of short-circuit failure in SiC MOSFETs under a bus voltage of 800 V, improving packaging or enhancing thermal management represents effective approaches to enhance their short-circuit tolerance under high bus voltages. Firstly, enhancing packaging is crucial. Choosing packaging materials resistant to high voltages or designing more robust packaging structures can mitigate the risk of device damage during short-circuit conditions. Furthermore, optimizing packaging design to enhance mechanical strength and electro-thermal performance is paramount. Secondly, enhancing thermal management systems facilitates the rapid dissipation of heat generated by the device, lowering device temperature and mitigating the impact of thermal stress, thereby reducing the risk of device damage due to abrupt temperature increases. The combined implementation of these measures effectively enhances the short-circuit tolerance of SiC MOSFETs under high bus voltages, ensuring their stable and reliable operation.
5. Conclusion
In this work, the unique short-circuit failure mechanisms of 1.2 kV class planar silicon carbide (SiC) MOSFETs were meticulously examined. The empirical findings suggest that, under a 400-volt direct current (DC) bias, the principal etiology of gate short-circuiting is attributed to inter-layer delamination precipitated by mechanical stress. Computational simulations corroborate that the device temperature, during a 400 V short-circuit condition, is predominantly localized within the JFET region, soaring up to 1300 K. This extreme temperature induces the aluminum to transition into a liquid state, establishing a conductive pathway along the fracture between the gate and the source, culminating in erratic device performance. On the contrary, under an 800 V DC bias, the failure mechanism differs from the traditional device failure mechanisms associated with the activation of parasitic transistors. It is believed to be a degradation of the gate oxide caused by the hot carrier effect. This degradation impedes the device's ability to shut off, triggers thermal runaway, and ultimately leads to device burnout.
[8] G Romano, L Maresca, M Riccio et al. Short-circuit failure mechanism of SiC power MOSFETs. 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC’s (ISPSD), 345(2015).