Contents
2022
Volume: 52 Issue 4
32 Article(s)
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A High Power Efficient Flash ADC Based on 4 Fold Time-Domain Interpolation
LIU Jianwei, JIANG Junyi, YE Yaqian, YANG Manlin, WANG Peng, WANG Yuxing, FU Xiaojun, and LI Ruzhang
A 6-bit 3.4 GS/s flash ADC was designed in a 65 nm CMOS process based on the 4 fold time-domain interpolation technique which allowed the reduction of the number of comparators from the conventional 2N-1 to 2N-2 in a N-bit flash ADC. The proposed scheme achieved effectively a 4 fold interpolation factor with simple SR-A 6-bit 3.4 GS/s flash ADC was designed in a 65 nm CMOS process based on the 4 fold time-domain interpolation technique which allowed the reduction of the number of comparators from the conventional 2N-1 to 2N-2 in a N-bit flash ADC. The proposed scheme achieved effectively a 4 fold interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage, where only offset between the 2N-2 comparators needed to be calibrated. The offset in SR-latches was within ±0.5 LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The prototype achieved 3.4 GS/s sampling frequency with 5.4 bit ENOB at Nyquist and consumed 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/(conv·step)..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 519 (2022)
Advances in Analog to Digital Converters for Sensor Signal Acquisition
PENG Shuai, SHI Xingchen, ZHANG Jie, QI Huanhuan, and ZHANG Hong
The fast development of internet of things (IoT), artificial intelligence (AI) and other related applications relies on various sensors with high sensitivity, while the quality and efficiency of sensor’s signal acquisition depends largely on the performance of the analog-to-digital converter (ADC) in the sensor’s readoThe fast development of internet of things (IoT), artificial intelligence (AI) and other related applications relies on various sensors with high sensitivity, while the quality and efficiency of sensor’s signal acquisition depends largely on the performance of the analog-to-digital converter (ADC) in the sensor’s readout circuit. After introducing the characteristics and working principles of 2 typical types of fully integrated sensors, the advances of research conducted on the ADCs for sensor signal acquisition were discussed in detail in this paper, including the operation theories, advantages and disadvantages, application scope and development dynamics of four ADC categories that were widely investigated and applied: Σ-Δ ADCs, successive approximation ADCs, dual-slope ADCs and hybrid ADCs..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 525 (2022)
A Four-Channel 16 bit 250 MS/s A/D Converter
CHEN Xi, FU Dongbing, LIU Lu, and LI Fei
A 4-channel 16 bit 250 MS/s A/D converter was designed in a 0.18 μm CMOS process. In the converter, a time interleaved structure combined with pipelined structure was adopted, which consisted of reference, clock and digital correction units. The chip tested results showed that the dynamic specification achieved a SNR oA 4-channel 16 bit 250 MS/s A/D converter was designed in a 0.18 μm CMOS process. In the converter, a time interleaved structure combined with pipelined structure was adopted, which consisted of reference, clock and digital correction units. The chip tested results showed that the dynamic specification achieved a SNR of 73 dBFS and a SFDR of 90 dBFS with digital calibration. The ADC channel power was 0.25 W, and the corresponding figure-of-merit (FoM) was 22 fJ/(conv·step)..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 533 (2022)
A Charge Pump for Clock Management Circuit of Analog-to-Digital Converters
ZHOU Qianneng, LI Heng, LI Hongjuan, ZHANG Hongsheng, YANG Hong, and TANG Zhengwei
A charge pump for clock management circuit of analog-to-digital converters (ADC) was designed in a 0.13 μm CMOS process. By adding transmission gates between the cascode charge-discharge current source and its bias circuit, the generation of leakage current was effectively suppressed when the charge pump was turned offA charge pump for clock management circuit of analog-to-digital converters (ADC) was designed in a 0.13 μm CMOS process. By adding transmission gates between the cascode charge-discharge current source and its bias circuit, the generation of leakage current was effectively suppressed when the charge pump was turned off. By adopting the current source enhanced technique, the impedance of charge-discharge current branch of charge pump was effectively improved, and the influence of channel-length modulation effect was suppressed, so the current matching performance of charge pump was effectively improved. Simulation results showed that the charge-discharge current mismatch was less than 1% with the output voltage varied from 0.13 V to 0.93 V under the condition of 1.2 V power supply voltage and 20 μA output current..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 539 (2022)
Research on MDAC Capacitance Mismatch Calibration Based on Pipelined ADC
LI Kun, YE Mingyuan, WAN Shuqin, and HE Qiuxiu
A foreground digital calibration technology for pipelined ADC was introduced. The calibration was mainly aimed at the sampling capacitor mismatch in MDAC, which increased the nonlinearity of ADC output. The proposed foreground digital calibration technology used the relative deviation of the integral nonlinearity of thA foreground digital calibration technology for pipelined ADC was introduced. The calibration was mainly aimed at the sampling capacitor mismatch in MDAC, which increased the nonlinearity of ADC output. The proposed foreground digital calibration technology used the relative deviation of the integral nonlinearity of the ADC output to extract the error, and used a simple multi-channel selection operation unit to compensate the error. On this basis, Verilog HDL was used to realize RTL level description, and the circuit was taped out successfully. Simulation and test results showed that the proposed calibration algorithm could improve the output performance of ADC..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 544 (2022)
A Capacitor Mismatch Detection and Digital Calibration Technique for SAR ADC
WANG Wei, LIU Bowen, CHIO U-Fat, ZHANG Dingdong, ZHANG Shan, and XIONG Deyu
In order to solve the non-linearity errors due to the parasitic capacitors and random mismatches of the capacitive DAC array in the high-resolution applications of SAR ADC, this paper proposed a low-complexity capacitor mismatch detection and calibration technique for a differential capacitive DAC in the SAR ADC. The cIn order to solve the non-linearity errors due to the parasitic capacitors and random mismatches of the capacitive DAC array in the high-resolution applications of SAR ADC, this paper proposed a low-complexity capacitor mismatch detection and calibration technique for a differential capacitive DAC in the SAR ADC. The capacitor mismatches were detected with comparator and capacitors in SAR ADC itself without extra analog circuit. The obtained mismatch values would be used to correct bit weight of the capacitors in the DAC. AMS simulation result showed that the ENOB of 16-bit SAR ADC with capacitor mismatch increased from 10.74 bit to 15.38 bit..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 550 (2022)
A Digital Decimation Filter ofΣ-Δ ADC with Ultra-Low Power and Small Area
SHEN Zesheng, LIU Yuntao, FANG Shuo, and WANG Yun
This research presented a digital decimation filter with ultra-low power and small area in the audio signal Σ-Δ analog-to-digital converters. The filter consisted of the cascaded integrating comb filter, the low order compensator, and the all-pass polyphase IIR filter. Compared with the conventional FIR filter, it contThis research presented a digital decimation filter with ultra-low power and small area in the audio signal Σ-Δ analog-to-digital converters. The filter consisted of the cascaded integrating comb filter, the low order compensator, and the all-pass polyphase IIR filter. Compared with the conventional FIR filter, it contained lower orders and hardware complexity. Meanwhile, it could achieve high decimation, ultra-low passband ripple, high stopband attenuation and approximately linear phase. The overall effective bandwidth was 20 kHz, and the decimation factor was 128. The ASIC design was implemented in a 0.18 μm CMOS process. The digital layout area was 0.37 mm2, and the power was 125 μW. The SNR reached 98.79 dB, and the effective accuracy achieved 16 bit. Compared with that of the decimation filter of traditional FIR structure, the area of the proposed digital decimation filter was reduced by 60% and the power consumption was cut down by 20%..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 555 (2022)
An Anti-TID Radiation Bandgap Voltage Reference
HU Yongfei, WANG Zhongyan, YANG Yang, DU Yubin, and LIU Honghong
An anti-TID radiation bandgap voltage reference was designed in a standard CMOS IC process. The intrinsic weakness of traditional bandgap framework in radiation situation was analyzed. The resistance of the bandgap voltage reference to total dose radiation was improved by taking of advantages of the characteristics thaAn anti-TID radiation bandgap voltage reference was designed in a standard CMOS IC process. The intrinsic weakness of traditional bandgap framework in radiation situation was analyzed. The resistance of the bandgap voltage reference to total dose radiation was improved by taking of advantages of the characteristics that the diode positive guide voltage was less affected by current. The bandgap voltage reference consisted of a startup circuit, a BGR core circuit and a self-bias circuit. The bandgap voltage reference was integrated in a 12 bit 100 kS/s sampling rate A/D converter as a unit, and the ADC was fabricated and tested. The results showed that the output voltage of the reference changed little after the total dose radiation test. Under the -55 ℃~125 ℃ temperature range, the temperature drift coefficient was 1.53×10-5/℃ before total dose radiation, and it was 1.71×10-5/℃ after total dose radiation..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 562 (2022)
A Bandgap Reference Circuit with High Voltage Input and High PSRR
WANG Yiwei, SUN Jiang, YE Wenxia, CHEN Ningkai, LEI Xinyu, and XIAN Wenqi
In high voltage wide input range chips, the high voltage power generally is not directly used as the power supply of the bandgap reference circuit. A Zener diode and source follower are always used to generate a low-voltage power supply for the bandgap in traditional scheme. However, the low-voltage power supply is fluIn high voltage wide input range chips, the high voltage power generally is not directly used as the power supply of the bandgap reference circuit. A Zener diode and source follower are always used to generate a low-voltage power supply for the bandgap in traditional scheme. However, the low-voltage power supply is fluctuated easily, which reduces the PSRR (power supply rejection ratio) of the bandgap. When the power supply of the bandgap is generated by the feedback loop, the reference may obtain a high PSRR performance. In this paper, a bandgap circuit with a wide input range of 5~65 V was proposed for the applications of bucks, motor drivers or analog ASIC chips. The closed-loop negative feedback circuit generated a low voltage power supply and a 1.2 V reference voltage. The power of the bandgap circuit was determined by the VGS of the PMOS, and the current of the PMOS was generated by the bandgap circuit. Therefore, the low voltage power supply made no reference to input voltage, which improved the PSRR of the reference voltage. The circuit was composed of a preprocessing circuit, a start-up circuit and a bandgap circuit. No additional mask layer and Zener diode were used in this design, which reduced the circuit cost. Under CSMC 0.25 μm BCD process, this design achieved a bandgap reference voltage which linear adjustment rate was 0.000 091%, PSRR under low frequency was -160 dB@100 Hz and the temperature coefficient was 2.8×10-5/℃. The reference voltage variation was less than 1 μV when input voltage varied in the range of 5~65 V..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 566 (2022)
Design of a Four-Quadrant 14-bit Multiplying D/A Converter
LEI Langcheng, LUO Yanxin, LIU Honghong, DU Yubin, GAO Weiqi, ZHANG Jun, WU Qiuxia, and FU Dongbing
A 14-bit multiplying D/A converter was designed. A piecewise current mode R-2R resistor network structure with high 3-bit thermometer code and low 11-bit binary code was adopted to avoid the disadvantages of large switch size and difficult layout matching of high resolution binary current mode R-2R resistor network. ThA 14-bit multiplying D/A converter was designed. A piecewise current mode R-2R resistor network structure with high 3-bit thermometer code and low 11-bit binary code was adopted to avoid the disadvantages of large switch size and difficult layout matching of high resolution binary current mode R-2R resistor network. The circuit was fabricated in a mixed signal CMOS process. The measured DNL was within ±0.5 LSB, and the INL was within ±0.8 LSB, which was suitable for the applications of industrial control and instrumentation..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 572 (2022)
A 14-bit 85 MS/s Pipelined ADC
ZHOU Xiaodan, SU Chen, LIU Tao, LI Xi, FU Dongbing, and LI Qiang
A 14-bit 85 MS/s pipelined analog-to-digital converter (ADC) was designed and implemented in a 0.18 μm CMOS process. Several techniques such as SHA-less front-end and amplifier sharing had been adopted to reduce the ADC’s power consumption and area. Under 3.3 V power supply, 85 MHz clock and 70 MHz sine input, the ADC A 14-bit 85 MS/s pipelined analog-to-digital converter (ADC) was designed and implemented in a 0.18 μm CMOS process. Several techniques such as SHA-less front-end and amplifier sharing had been adopted to reduce the ADC’s power consumption and area. Under 3.3 V power supply, 85 MHz clock and 70 MHz sine input, the ADC achieved an SNR of 67.9 dBFS and an SFDR of 82.2 dBFS without calibration. It consumed 322 mW with an area of 0.6 mm2, which was suitable for communication systems where lower power ADCs were needed..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 577 (2022)
A Radiation Hardened Four Channel High Voltage 12-bit DAC
WANG Zhongyan, HU Yongfei, and GAO Weiqi
A quad high voltage radiation hardened voltage output 12-bit DAC was designed and implemented in a 0.6 μm standard CMOS process with high and low voltage devices. The R-2R ladder network and high-voltage multistage folding-cascode operational amplifier which operated as a buffer output was proposed. This structure realA quad high voltage radiation hardened voltage output 12-bit DAC was designed and implemented in a 0.6 μm standard CMOS process with high and low voltage devices. The R-2R ladder network and high-voltage multistage folding-cascode operational amplifier which operated as a buffer output was proposed. This structure realized the good monotonicity of DAC and improved its radiation resistance. The chip size was 5.80 mm×3.70 mm. The test results showed that the output range of the DAC was -2.5~2.5 V, the power consumption was 26.95 mW, the DNL was 0.41 LSB, the INL was 0.34 LSB, the settling time was 6.5 μs, and the INL compatibility was 0.11 LSB at ±5 V power supply..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 582 (2022)
A Method of Calibrating Interstage Gain of Pipeline A/D Converter by Piecewise Shift Technique
LEI Langcheng, WANG Zhongyan, ZHAN Yong, LIU Honghong, HU Yongfei, DU Yubin, and FU Dongbing
The gain mismatch between sampling capacitance and feedback capacitance in pipeline A/D converters was analyzed. The relationship between the finite gain of operational amplifier and pipeline residual output, as well as the output of A/D converter, was investigated. So an accurate system model was established. Based onThe gain mismatch between sampling capacitance and feedback capacitance in pipeline A/D converters was analyzed. The relationship between the finite gain of operational amplifier and pipeline residual output, as well as the output of A/D converter, was investigated. So an accurate system model was established. Based on the Verilog-A behavioral model of 14 bit pipelined ADC, the digital output of pipelined ADC was shifted piecewisely in digital domain. When the inter-stage gain error of first stage reached ±0.012 5, the SNR was only 62 dB before calibration, and it was 85 dB after calibration. The proposed calibration method could compensate for the discontinuity of digital output and the linearity degeneration caused by inter-stage gain errors..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 587 (2022)
A Low Latency Folding and Interpolation 12 bit 1.5 GS/s ADC
XU Mingyuan, FU Dongbing, ZHU Can, ZHANG Lei, WANG Yan, and LI Liang
Based on a 4-stage cascade folding interpolation architecture, a 12-bit ADC was presented. The circuit was designed in a 0.18 μm SiGe BiCMOS process. The single core achieved a conversion speed of 1.5 GS/s, the output interface was 2-lane LVDS, and the latency was less than 7 ns. The front-end sample/hold circuit and fBased on a 4-stage cascade folding interpolation architecture, a 12-bit ADC was presented. The circuit was designed in a 0.18 μm SiGe BiCMOS process. The single core achieved a conversion speed of 1.5 GS/s, the output interface was 2-lane LVDS, and the latency was less than 7 ns. The front-end sample/hold circuit and folding interpolation quantizer adopted pure bipolar design, which could achieve 12 bit quantization accuracy without trimming. Finally, the design points and test results of the published layout were given..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 597 (2022)
Design of a 10-bit High Speed Pipeline-SAR Hybrid ADC
LI Xiao, LI Xiaoran, ZHANG Hao, YANG Jiaheng, and ZHANG Lei
A 10-bit 100 MS/s pipeline-SAR hybrid ADC without residue amplifier was designed in a 180 nm CMOS process. A two-stage pipeline-SAR hybrid structure was adopted, with the 4-bit most significant bit (MSB) conversion completed in the first stage and the 6-bit least significant bit (LSB) conversion completed in the secondA 10-bit 100 MS/s pipeline-SAR hybrid ADC without residue amplifier was designed in a 180 nm CMOS process. A two-stage pipeline-SAR hybrid structure was adopted, with the 4-bit most significant bit (MSB) conversion completed in the first stage and the 6-bit least significant bit (LSB) conversion completed in the second stage. In order to reduce the power consumption, the monotonic switching procedure was used, and the residue voltage was delivered from the first stage to the second one by charge sharing. The asynchronous timing control logic was applied to further improve the energy efficiency and the conversion speed. The post-layout simulation results showed that this ADC achieved an ENOB of 9.39 bit and a SNDR of 58.34 dB at 100 MS/s Nyquist sampling rate. The power consumption was 5.9 mW with a 1.8 V supply voltage..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 603 (2022)
A 16-bit High-Precision Segmented-Resistance DAC
ZHANG Haoran, JIAO Zihao, SHENG Wei, ZHANG Yuxin, CAO Yanjie, and CHEN Minqi
Based on a 0.5 μm BCD technology, a 16-bit high-precision segmented-resistance digital-to-analog converter (DAC) was designed. According to the general resistance mismatch feature in integrated circuit process, the DAC had “4+12” architecture, and it was divided into temperature coding part and binary coding part. All Based on a 0.5 μm BCD technology, a 16-bit high-precision segmented-resistance digital-to-analog converter (DAC) was designed. According to the general resistance mismatch feature in integrated circuit process, the DAC had “4+12” architecture, and it was divided into temperature coding part and binary coding part. All the resistors in this DAC were high-impedance, which reduced the mismatch in the DAC switch architecture as well as its whole power dissipation. The DAC had a compact architecture and a small layout area of 2.397 6 mm2. Combined with the results after post-simulation, the layout was modified, which made the DAC have a low differential non-linearity (DNL). Moreover, its calibration part could make it lower. The test results showed that the DAC had a spurious free dynamic range of 57.72 dB, a DNL of 0.5 LSB, a INL of 1 LSB, and a power dissipation of 1.5 mW when its input was 10 kHz sine digital wave data..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 608 (2022)
New Trends in GaN Technology Development
SHAN Yuehui, LIAN Luwen, GAO Yuan, and LAI Fan
Gallium nitride (GaN) is a typical representative of the third generation of semiconductors, which has received wide attention from academia and industry, and is becoming one of the key technologies relied upon to surpass Moore's law in the future. In terms of radio frequency (RF) GaN technology, the two major applGallium nitride (GaN) is a typical representative of the third generation of semiconductors, which has received wide attention from academia and industry, and is becoming one of the key technologies relied upon to surpass Moore's law in the future. In terms of radio frequency (RF) GaN technology, the two major application-growing industries in telecom and national defense, especially the military sector's increasing demand for advanced radar and communication systems, has driven development of RF GaN devices to higher frequency, higher power and higher reliability. This paper described GaN RF/microwave HEMT, millimeter wave transistor and MMIC (monolithic microwave integrated circuit), the GaN devices space application reliability and radiation hardening and other technical development of the domain. In power electronics, the demand for efficient, green and intelligent energy pulled GaN power electronics, power converters to the directions of fast charging, high efficient and small size. This paper briefly described the commercial and development progress of GaN power devices applied to pure electric and hybrid electric vehicles (EV/HEV), industrial manufacturing, telecommunications infrastructure and other occasions. At the frontier of digital computing, especially quantum computing, GaN is one of the technologies with promising applications, so several highlights of GaN computing and cryogenic electronics research were presented. In summary, this paper gave a general description of the latest trends in several areas of GaN technology development, and sketched out the rough lines of technology development..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 614 (2022)
Progress on Cu/SiO2 Wafer-Level Hybrid Bonding Technology for 3D Integration Applications
LIU Yiqun, ZHANG Hongwei, and DAI Fengwei
Cu/SiO2 hybrid bonding technology is considered as an ideal solution for 3D integration of chips and high-density electrical interconnection. Both dielectric bonding and metal bonding should be taken into consideration in such technology. Therefore, few native self-developed hybrid bonding achievements with simple procCu/SiO2 hybrid bonding technology is considered as an ideal solution for 3D integration of chips and high-density electrical interconnection. Both dielectric bonding and metal bonding should be taken into consideration in such technology. Therefore, few native self-developed hybrid bonding achievements with simple process and low cost have been developed in Chinese mainland. In this paper, existing wafer level bonding technologies were summarized, including direct bonding, activated bonding and solid-liquid inter-diffusion bonding. And the possibility of their application in hybrid bonding was deeply analyzed. Moreover, recent research progresses of Cu/SiO2 hybrid bonding technologies were further summarized. Finally, the key factors to realize this technology were analyzed in principle. This review will provide a guidance for the domestic semiconductor industry to occupy this promising technical field..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 623 (2022)
Research on Packaging of Thermoelectric MEMS Microwave Power Sensors
TANG Meng, YU Wenting, ZHU Yucheng, SUN Lilu, HUA Rui, and WANG Debo
In order to study the performance of the thermoelectric MEMS microwave power sensor after packaging, a package of COB technology was proposed. Firstly, the microwave characteristics before and after packaging were simulated by finite element simulation software HFSS. Then, the thermoelectric MEMS microwave power sensorIn order to study the performance of the thermoelectric MEMS microwave power sensor after packaging, a package of COB technology was proposed. Firstly, the microwave characteristics before and after packaging were simulated by finite element simulation software HFSS. Then, the thermoelectric MEMS microwave power sensor was fabricated in a GaAs MMIC technology, and the prepared chip was packaged. Finally, the microwave characteristics and output characteristics of the sensor were measured before and after packaging. The measured results showed that the return loss after packaging was less than -10.50 dB in the frequency range of 8~12 GHz. The sensitivity before packaging was 0.16 mV/mW@10 GHz, and the sensitivity after packaging was 0.18 mV/mW@10 GHz. After the thermoelectric microwave power sensor was packaged, the output voltage still had a good linearity with the input power. Therefore, this work had certain reference value and guiding significance for the research on the packaging of thermoelectric MEMS microwave power sensors..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 635 (2022)
A Piezoelectric Energy Harvester with Right Angle Helical Cantilever Structure
ZHOU Jiacheng, XUE Zhicheng, and WANG Debo
A piezoelectric energy harvester with a right angle spiral cantilever structure which had a 2π radian was proposed. This design could reduce the resonant frequency on the one hand and improve the efficiency of energy collection per unit volume on the other hand. The thickness of the cantilever beam was 2 mm, the width A piezoelectric energy harvester with a right angle spiral cantilever structure which had a 2π radian was proposed. This design could reduce the resonant frequency on the one hand and improve the efficiency of energy collection per unit volume on the other hand. The thickness of the cantilever beam was 2 mm, the width was 6 mm, and the overall size was 22 mm×26 mm. When the acceleration of 0.1g excitation was applied, the simulated outpour voltage was 1.95 V, the output voltage measured was 1.8 V, and the relative voltage error was 7.7%. The simulated resonant frequency was 269 Hz, the measured resonant frequency was 265 Hz, and the relative frequency error was 1.5%. The theoretical output power was 7.04 μW, the measured output power was 5.79 μW, and the relative power error was 17.8%. This piezoelectric energy harvester had a wide application prospect in power supply of portable microelectronic devices..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 640 (2022)
A Novel Phase and Speed Combinatorial Motor Control Structure
CHEN Can, Lü Guo, YANG Liuqing, PANG Youbing, and MA Chaoji
Aiming at the disadvantage that the angle error of motor rotation will increase with time because of the deviation between actual speed and expect speed in the speed feedback motor control system, a control structure combining phase with speed was proposed. A phase loop was added to the speed loop. By inputting a squarAiming at the disadvantage that the angle error of motor rotation will increase with time because of the deviation between actual speed and expect speed in the speed feedback motor control system, a control structure combining phase with speed was proposed. A phase loop was added to the speed loop. By inputting a square wave signal to the motor system with steady frequency, the motor speed was controlled by the combinatorial loop circuit to reach the expect speed. The angle of rotation was also controlled to synchronize the phase of the reference square wave signal, so the angle error of motor rotation would not increase with time any more. The combination principle of the scheme was introduced in detail,and an actual motor control system was built for verification. Under the circumstance of 100 Hz square wave signal input, the actual motor control system achieved the following characteristics: stabilization time ≤2 s, speed accuracy in steady state was 6 000±10 r/m, and phase error ≤±50 μs..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 646 (2022)
A 6~18 GHz Wideband High Accuracy Active Phase Shifter
NAN Yaqi, LEI Xin, FAN Chao, and GUI Xiaoyan
A 6-bit wideband high accuracy active phase shifter with 6~18 GHz frequency range was designed. The passive baluns, poly-phase filters, vector-sum cells and digital controlled cells were included in the proposed phase shifter. This phase shifter was implemented in a 55 nm CMOS process. The overall chip size was 1.29 mmA 6-bit wideband high accuracy active phase shifter with 6~18 GHz frequency range was designed. The passive baluns, poly-phase filters, vector-sum cells and digital controlled cells were included in the proposed phase shifter. This phase shifter was implemented in a 55 nm CMOS process. The overall chip size was 1.29 mm×0.9 mm, and the phase shifter core chip size was 1.02 mm×0.58 mm. The post-simulation results showed that the RMS gain variation was less than 1 dB, and the RMS phase error was less than 0.75° within 6~18 GHz frequency range. The input and output return losses were less than -8.5 dB and -10 dB, and the total power consumption was 20.7 mW. The relative bandwidth of the 6 bit phase shifter was 100%, covering C, X and Ku band. It was suitable for radar detection and other applications..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 651 (2022)
A Clock Data Recovery Circuit with Adaptive Loop Bandwidth Adjustment
CHANG Cheng, WEI Baolin, WEI Xueming, HOU Lingli, and XU Weilin
Aiming at the requirements of SONTE OC-192, PCIE3.0, USB3.2 and other protocols for jitter tolerance and loop stability time during serial clock data recovery, a half rate phase interpolation CDR circuit with adaptive loop bandwidth adjustment was proposed. The adaptive control circuit was designed to dynamically adjusAiming at the requirements of SONTE OC-192, PCIE3.0, USB3.2 and other protocols for jitter tolerance and loop stability time during serial clock data recovery, a half rate phase interpolation CDR circuit with adaptive loop bandwidth adjustment was proposed. The adaptive control circuit was designed to dynamically adjust the loop bandwidth in a timely manner to achieve fast loop stability during serial signal clock recovery and improve the jitter tolerance of the clock data recovery circuit. A compensated phase interpolation controller was added to further reduce the data reception BER. The CDR circuit was designed in a 55 nm CMOS process with a data input range of 8~11.5 Gbit/s. The random code PRBS31 was used. The simulation test results showed that the stabilization time was less than 400 ns, the input jitter tolerance was more than 0.55UI@10 MHz, and the power consumption was less than 23 mW..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 656 (2022)
3-D Equivalent Circuit Model of MEMS Microwave Power Sensors
YU Wenting, TANG Shuting, XIN Zehui, and WANG Debo
In order to obtain 3-D temperature distribution and time constant of a thermoelectric MEMS microwave power sensor, a 3-D equivalent circuit model was established. Firstly, the equivalent circuit model was established based on the equivalent relationship of thermal parameter and electrical parameter with the structural In order to obtain 3-D temperature distribution and time constant of a thermoelectric MEMS microwave power sensor, a 3-D equivalent circuit model was established. Firstly, the equivalent circuit model was established based on the equivalent relationship of thermal parameter and electrical parameter with the structural of sensor. Then the unit module of the equivalent circuit was analyzed theoretically. Finally, the temperature distribution and response time of the sensor were studied according to the 3-D equivalent circuit model. The sensitivity of the sensor is 0.076 mV/mW @10 GHz, and the time constant is 56.24 μs from the model. The measured results show that the sensitivity of the sensor is 0.06 mV/mW @10 GHz, and the time constant is 85 μs. The 3-D equivalent circuit model established in this paper can not only obtain the time constant of microwave power sensor, but also accurately obtain the heat dissipation in the substrate. Therefore, this work has a certain reference value for thermoelectric MEMS microwave power sensors..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 663 (2022)
A Broadband Low Phase Noise Low Spurious Σ-Δ Fractional-N Frequency Synthesizer
YAO Junjie, ZHANG Changchun, ZHANG Yu, ZHANG Ying, and YUAN Feng
A Σ-Δ fractional-N frequency synthesizer with broadband, low phase noise and low spurious was designed in a 65 nm CMOS process. Three voltage-controlled oscillators and a programmable frequency division link was adopted in the frequency synthesizer to achieve broadband output, and each voltage-controlled oscillator intA Σ-Δ fractional-N frequency synthesizer with broadband, low phase noise and low spurious was designed in a 65 nm CMOS process. Three voltage-controlled oscillators and a programmable frequency division link was adopted in the frequency synthesizer to achieve broadband output, and each voltage-controlled oscillator introduced an adaptive body-biasing technique to reduce the impact of PVT changes. A retiming unit was taken in the programmable frequency divider to synchronize the output, which improved the phase noise of the frequency divider. The automatic frequency calibration circuit adopted a structure that directly counted the voltage-controlled oscillator, which shortened the frequency lock time. A notch filter structure was added to the Σ-Δ modulator to reduce output quantization noise. The post simulation results showed that the frequency range of the quadrature signal that the frequency synthesizer could output was 0.2 ~ 6 GHz under 1.2 V power supply voltage. When the output frequency was 3.762 5 GHz, the phase noise was -113.59 dBc/Hz @1 MHz, the reference spurious was -59.3 dBc, and the power consumption was 91 mW..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 668 (2022)
Design and Implementation of a High Security and High Performance RSA Coprocessor
ZANG Shiping, XU Kejing, HU Yi, DU Pengcheng, and GAO Ying
In order to prevent the data from being tampered in power communication in smart grid, security chip is essential, and RSA algorithm is one of the most widely used public key algorithms. However, due to the high complexity and power consumption of hardware implementation, it is unable to take the performance, power conIn order to prevent the data from being tampered in power communication in smart grid, security chip is essential, and RSA algorithm is one of the most widely used public key algorithms. However, due to the high complexity and power consumption of hardware implementation, it is unable to take the performance, power consumption, security into account. In this paper, a high secure and high performance RSA coprocessor was designed. The security strategy proposed enhanced the coprocessor's ability to resist side channel attack, differential power attack and EMA electromagnetic attack. Two levels of algorithm optimization were used to improve the coprocessor performance, and the improved Montgomery modular multiplication algorithm combined with CIOS square algorithm and Karatsuba algorithm made the 1 024 bit RSA algorithm with protection have an area of 48 000 gates @30 MHz and a power consumption of 4.62 mW @30 MHz under UMC 55 nm process. The performance of API test on FPGA board was 709.3 kbit/s..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 675 (2022)
A High Efficiency Boost Converter Chip with MPPT Function for PV Cell
ZHU Xiwen, JIANG Qing, QIN Peng, XU Kaixuan, and ZHANG Yufeng
To improve the collection efficiency and environmental adaptability of PV cell, a high efficiency boost converter chip with MPPT function for PV cell was proposed. This circuit system included a new type of four-phase high efficiency charge pump module, an MPPT control circuit module which utilized a disturbance observTo improve the collection efficiency and environmental adaptability of PV cell, a high efficiency boost converter chip with MPPT function for PV cell was proposed. This circuit system included a new type of four-phase high efficiency charge pump module, an MPPT control circuit module which utilized a disturbance observation method, a feedback control module, a nA level current reference, and a detection circuit module. The chip was designed, simulated and manufactured in a 0.35 μm BCD process. The chip size was 3.15 mm×2.43 mm. The test results showed that when the PV cell output voltage was more than 0.5 V, the output voltage of the converter was raised to 3Vin, and the voltage conversion efficiency could reach 99.4%. The MPPT algorithm made the output power improve by 8.53%. When the output load current was 297 μA, the widest output PCE achieved 85.1%. The chip was highly efficient in boosting the output voltage of PV cells..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 681 (2022)
Design and Verification of a High Performance Second-Order Charge-Controlled Memristor Circuit
XIAO Li, JIN Xiangliang, YANG Jian, and HUANG Shishi
The traditional operational amplifier in the memristor equivalent circuit has problems such as high power consumption and large noise. To solve this problem, two extremely simplified operational amplifiers based on simplified differential pairs was designed. The power consumption and noise analysis of two simplified opThe traditional operational amplifier in the memristor equivalent circuit has problems such as high power consumption and large noise. To solve this problem, two extremely simplified operational amplifiers based on simplified differential pairs was designed. The power consumption and noise analysis of two simplified operational amplifiers and traditional operational amplifiers were carried out through simulation analysis. The results showed that this simplified operational amplifier circuit had the lowest power consumption and the best anti-noise performance when compared with three traditional operational amplifiers. The total power consumption was 15 mW, the equivalent output noise voltage was 11.55 nV·Hz-1/2, and the noise figure was 35.873 dB. Based on the two simplified operational amplifiers, a second-order charge-controlled memristor equivalent circuit was designed. Through theoretical analysis, circuit simulation, and the hardware circuit board-based experiment, the memristive characteristics of the equivalent circuit were analyzed and verified..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 689 (2022)
Research on Ultrasonic Detection and Validity Verification of LTCC Filter Micro-Delamination
ZHANG Yuxing, GONG Guohu, and HE Zhigang
The feasibility of ultrasonic scanning was studied in the micro-delamination detection of LTCC filter. Firstly, it was confirmed through theoretical calculations that the micro-delamination had an extremely high reflectivity to ultrasonic waves at the reference frequency, and the resolution requirements in the actual dThe feasibility of ultrasonic scanning was studied in the micro-delamination detection of LTCC filter. Firstly, it was confirmed through theoretical calculations that the micro-delamination had an extremely high reflectivity to ultrasonic waves at the reference frequency, and the resolution requirements in the actual detection were explained. Secondly, ultrasonic test was applied to the filter, specific test suggestions were provided, and the defect information was identified according to test results. Then, the sample profile was prepared, and the defects were located according to the acquired defect information. Finally, the FIB etching technology was utilized to verify the inspection results and confirm the feasibility of ultrasonic detection of filter micro-delamination defects..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 695 (2022)
A Short Circuit Current Limiting and Protection Circuit for High Side Switches
LI Hao, XIONG Ping, YANG Shihong, WANG XiaoJing, GENG Li, and LI Dan
A short circuit current limiting and protection circuit for high side switches was presented. The mode of secondary protection was adopted by the circuit. When the short circuit detection voltage was not zero and lower than the reference voltage, the grid source voltage was limited to suppress the current of the circuiA short circuit current limiting and protection circuit for high side switches was presented. The mode of secondary protection was adopted by the circuit. When the short circuit detection voltage was not zero and lower than the reference voltage, the grid source voltage was limited to suppress the current of the circuit. When the short circuit detection voltage was higher than the reference voltage, the power tube would be turned off after a time delay. The chip was fabricated in a 100 V 0.18 μm BCD process. The test results showed that the power transistor was in normal working state under the two conditions of working before short circuit and working after short circuit. The working voltage range of the circuit was 4~80 V, the short circuit delay time was about 200 μs, and the maximum sustainable output current could reach 80 A..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 700 (2022)
Study on Total-Ionizing-Dose Radiation Induced BV Degradation of High Voltage SOI pLDMOS
HUANG Keyue, WU Zhonghua, ZHOU Miao, CHEN Weizhong, WANG Zhao, and ZHOU Xin
The total-ionizing-dose radiation effect in high voltage SOI pLDMOS devices was studied. The degradation mechanism of breakdown voltage under different bias conditions was analyzed, fixed trap charges were introduced at the interface of different oxide layers using TCAD， and the effect of the total ionizing radiation dThe total-ionizing-dose radiation effect in high voltage SOI pLDMOS devices was studied. The degradation mechanism of breakdown voltage under different bias conditions was analyzed, fixed trap charges were introduced at the interface of different oxide layers using TCAD， and the effect of the total ionizing radiation dose was simulated. The results showed that the total dose radiation introduced radiation trap charges QBOX and QFOX at FOX and BOX. The QFOX elevated the transverse electric field near the drain and reduced the buried oxide electric field, shifting the breakdown location from the body to the surface, and leading to degradation of the breakdown voltage. The QBOX reduced the buried oxide electric field and reduced the buried oxide voltage drop, leading to degradation of the breakdown voltage..
Microelectronics
- Publication Date: Jan. 18, 2023
- Vol. 52, Issue 4, 706 (2022)
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