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- Photonics Research
- Vol. 2, Issue 3, A25 (2014)
Abstract
1. INTRODUCTION
A. Need for Optical Interconnect for Memory Interface
As the demand continues for higher performance servers or PCs, the bandwidth and capacity requirements of the main memory system is correspondingly growing [
Figure 1.Simulated eye diagrams of memory bus with 4 DIMMs in one DDR3 memory channel.
A registered dual in-line memory module (RDIMM) reduces the loading of command/address signals to improve SI, and a load reduced in-line memory module (LRDIMM) [
An impedance-matched bidirectional multidrop bus was suggested [
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Optical interconnect technology is a promising candidate to scale up dynamic random-access memory (DRAM) interface over
B. Need for Bulk-Si-Based Optical Interconnect
Silicon photonics can provide a cost-efficient optical channel by fabricating the photonic devices on a silicon substrate using already-mature complementary metal-oxide semiconductor (CMOS) technology and can also be one of the most viable technologies for central processing unit (CPU)–memory optical interconnects. Over the past decades, there have been great achievements in silicon photonics [
Thus, we propose to implement photonic devices on a bulk-Si platform for lower material cost and capability of integrating photonic devices with electronic circuits on bulk-Si substrate. There are several related works for bulk-Si approaches, where optical waveguides are defined with the poly-Si core layer on the oxide undercladding [
In this paper, we introduce bulk-Si photonics technology using local-crystallized Si-core waveguides on oxide for the interface between CPU and DRAMs. In Section
2. BULK-SI PHOTONICS PLATFORM
A. Local Crystallization of Amorphous Silicon (Waveguide and Coupler)
The most basic building block of silicon photonics is the waveguide through which light propagates from one point to another point. In order to fabricate the waveguide and other optical devices on the bulk-Si substrate, a lower-refractive-index cladding for optical confinement is required under the crystalline silicon layer.
Figure
Figure 2.Process steps for fabricating the waveguide on a bulk-Si substrate. C-Si: crystallized silicon, PR: photoresist.
Figure 3.SEM images after crystallization of deposited a-Si depending on annealing condition: (a) low, (b) medium, and (c) high temperature.
Figure
Figure 4.VSEM images of fabricated waveguide on the bulk-Si substrate.
We measured the propagation loss of fabricated waveguides (more than five samples at each length) by using a cut-back method. The average and standard deviation of the waveguide loss were measured to be 6.1 dB and
Another approach to crystallize amorphous silicon is the laser induced epitaxial growth (LEG). In this the liquid phase epitaxy method, a huge amount of radiation energy is absorbed by an amorphous Si layer during several tens to several hundreds of nanoseconds. As a result, the Si layer is melted and then recrystallized during the solidification [
Figure
Figure 5.Cross section of inlaid structure for LEG process.
Figure
Figure 6.High resolution TEM image and diffraction pattern: (a) SPE-Si and (b) LEG-Si.
B. Active Components: Modulator
The modulator is a device that converts the voltage or current change of an electrical signal to the change of output light intensity. Depending on the type of electron–photon interaction, modulators can be either electro-optical (EO) modulators or electroabsorption (EA) modulators. EO modulators are based on the index change caused by the carrier density change, while EA modulators are based on the field-induced absorption change. In terms of how the index change is related to the intensity change, EO modulators can be implemented by a Mach–Zehnder interferometer (MZI) type or by microring resonator (MRR) type. We describe the progress of both MZI modulators and MRR modulators.
The bulk-Si MZI modulator design follows that of typical carrier-injection-type p–i–n diodes except that the oxide undercladding is locally formed under the modulator [
Figure 7.(a) Cross-sectional diagram of the active part of the bulk-Si MZI modulator. (b) SEM image of the dotted region in (a). The inclined arrows indicate the boundary of the local oxide undercladding formed underneath the active part. (c) Microscope image. Dotted line indicates the location of (a) and (b).
The forward on-resistance was measured to be
For AC measurements, a non-return-to-zero (NRZ) pseudorandom binary sequence (PRBS) signal from a pulse pattern generator (PPG) was applied to one arm of the MZI modulator. A 1550 nm laser light source was coupled to the modulator via the grating coupler. The modulated optical signal was amplified by an erbium-doped fiber amplifier and bandpass-filtered to remove the amplified spontaneous emission. Then, the eye diagram was observed by a digital communication analyzer (DCA) with a 20 GHz bandwidth.
Figure
Figure 8.Optical eye diagrams at NRZ
The bulk-Si MRR modulator is described in Fig.
Figure 9.(a) Lateral design of racetrack modulator with metal boundary illustrated. (b) Eye diagram at 1559.24 nm with
C. Active Components: Photodetector
The photodetector is a device that converts input light intensity to electrical current. We introduce two different types of photodetector depending on how the light reaches the Ge: a surface-type photodetector and a waveguide-type photodetector. The surface-type photodetector can allow simpler process steps and larger alignment tolerance with fibers, while the waveguide-type photodetector is a mandatory component for wavelength division multiplexing or integration with electronics.
The surface-type photodetector accepts input light vertically from outside the device and generates photocurrent using a reverse-biased p–i–n junction, shown in Figs.
Figure 10.(a) Microscope photography, (b) SEM image, and (c)
The waveguide-type photodetector receives the optical signal from the Si waveguide that is laterally butt-coupled to the Ge region, as illustrated in Figs.
Figure 11.Schematic diagram of waveguide-type photodetector (a) along the light propagation, and (b) perpendicular to the light propagation. (c) VSEM image, (d)
D. Integration with Electronics
Monolithically integrating photonics with electronics can provide invaluable advantages for lower cost and lower power consumption for many applications.
Figure
Figure 12.(a) Optical microscope image of EPIC, (b) schematic of EPIC vertical structure, and (c) SEM images of transistors, modulator, and Ge photodiode.
Figure
Figure 13.Performance of the bulk-Si photonic devices integrated into the DRAM process.
3. OPTICAL LINK VERIFICATION
A. Possibility of Multidrop Bus Topology at 10 Gb/s
We tested a
Figure 14.
Figure
Figure 15.Electrical eye diagram measured at channel 1–4 receiver: (a) through (d) with the transmitter in a QFP package, (e) through (h) on a bare die.
B. Link Demonstration with Integrated PICs
We fabricated a PIC integrating the photonic devices introduced in Section
Figure
Figure 16.Block diagram of an optical interconnect transceiver. PD: photodiode, MOD: modulator.
Die photographs and a packaged transceiver chip are shown in Fig.
Figure 17.(a) Photograph of dies for PIC and EIC. (b) Photograph of copackaged optical transceiver chip.
The optical link is verified at various data rates using the setup in Fig.
Figure 18.(a) Experiment setup to verify link operation using two optical transceivers. (b) and (c) Eye diagram at the output of optical amplifier at data rate of 1.5 and
4. DDR3 MEMORY ACCESS TEST
To verify memory read/write operation through the optical interface, two transceiver chips are inserted between the memory control board and the DRAM—one at the controller side and the other at the DRAM side, shown in Fig.
Figure 19.(a) Photograph and (b) block diagram of the experiment setup to verify optically interconnected DRAM interface. A: optical amplifier.
A 32 bit sequential data pattern, for each of four data lanes, is written to the DRAM over an optical channel through four consecutive eight-burst write commands synchronized to a 400 MHz control clock signal. Then, four consecutive eight-burst read commands are given to the DRAM at the same address, and the output data is verified to be same as written at the corresponding DQ pin.
Oscilloscope traces for DQ0 operation are shown in Fig.
Figure 20.(a) Block diagram of the experiment setup and (b) oscilloscope traces for DQ0 (blue) and DQS signals (red) at controller side and DRAM side with output enable signals (green).
5. SUMMARY AND FUTURE DIRECTION
We presented photonics technology based on bulk-Si substrate for Si photonics applications including DRAM optical interface. Two different approaches, SPE and LEG, were addressed to implement the local-crystallized Si waveguide on bulk-Si substrate. Starting from the passive elements such as the waveguide and coupler, the progress on active devices including the modulator and photodetector was summarized. As the performance gap between the bulk-Si devices and the conventional SOI devices is gradually narrowing, the cost efficiency of the bulk-Si platform is becoming a larger advantage. The process of integration of PIC with EIC was demonstrated using a 65 nm DRAM periphery process on 300 mm wafers, which proved the possibility of being seamlessly integrated with various CMOS devices thanks to the homogeneous substrate. We used the bulk-Si photonic devices to show the feasibility of a high-speed multidrop interface, especially for CPU-DRAM interface. The MZI modulators and commercial APDs demonstrated four-drop operation at
For a future research direction, we can consider the following three issues: first, in order to further reduce the optical link latency, supporting uncoded data is desired to remove the time for line coding such as 8b10b or 64b66b and to reduce the power consumption of transceivers that are always on. For this purpose, the photonic devices are expected to work over a broad frequency range for DC-coupled links. Second, we need to lower the loss of photonic devices to remove the optical amplifier in the link and, accordingly, reduce the latency and power consumption. Third, a cost-efficient way to align the fiber to the VGC should be devised, because otherwise expensive active alignment can delay the adoption of optical interconnects for the cost-sensitive memory interface application.
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