In pedestrian positioning methods, the strapdown inertial navigation system requires processing data from the Inertial Measurement Unit(IMU) sensors, and the position of the pedestrian is obtained after algorithmic processing, thus placing high demands on the real-time performance and low power consumption of the chip. Since most pedestrian positioning algorithms are developed based on floating-point sensor data, the terminal device is generally required to handle floating-point data. The fifth-generation Reduced Instruction Set Computer(RISC-V) architecture, as an open-source architecture, can save on architectural licensing fees and has a wide range of applications in the field of the Internet of Things. Moreover, its floating-point(F) and vector(V) high-performance extension instructions can well meet the real-time requirements of pedestrian positioning algorithms. In response to the specific performance requirements of the pedestrian positioning system, a System on Chip (SoC) for pedestrian positioning based on a floating-point core vector processor optimized RISC-V architecture is proposed and verified in actual systems. A performance comparison analysis with several quasi-32-bit architecture RISC-V processors and standard processor schemes of algorithm-specific IPs (locate_IP) generated by High-Level Synthesis(HLS) components shows that the design has achieved a 34-fold improvement in performance and a 5.6-fold improvement in energy efficiency, meeting the requirements of micro terminals.