In order to solve the problem of poor equalization ability of traditional continuous time linear equalizer(CTLE), a new 25 Gb/s CTLE circuit based on 40 nm complementary metal oxide semiconductor(CMOS) technology is proposed, which adopts parallel inductance peaking, negative capacitance zero compensation and output buffering technology. The influence of shunt inductance peaking and passive devices on CTLE frequency characteristics is introduced. Finally, the new CTLE circuit is simulated. The simulation results show that when the data transmission rate is 25 Gb/s, the equalized bandwidth of the CTLE extends from 8.5 GHz to 21.3GHz. The peak-to-peak differential voltage of the output signal is 410 mV, and the power consumption is 8.62 mW. The overall circuit layout area is 667 μm×717 μm, which has the characteristics of low power consumption and small area.