• Study On Optical Communications
  • Vol. 46, Issue 1, 17 (2020)
FU Yi-wen1, JIANG Lin2, SHAN Rui1, WU Hao-yue1, and Fan Meng1
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    DOI: 10.13756/j.gtxyj.2020.01.004 Cite this Article
    FU Yi-wen, JIANG Lin, SHAN Rui, WU Hao-yue, Fan Meng. Implementation of Photoelectric Hybrid Interconnect Prototype System for Reconfigurable Video Array Processor[J]. Study On Optical Communications, 2020, 46(1): 17 Copy Citation Text show less

    Abstract

    High Efficiency Video Coding (HEVC) standard puts higher requirements on system bandwidth while improving the coding performance. The traditional electrical interconnection method has the problems of small bandwidth and large delay. Therefore, the high bandwidth and low power consumption of the optical interconnection propose a new solution for on-chip resource data communication. However, due to the limitation of the process level, the integrated optical device cannot be implemented inside the Field Programmable Gate Array (FPGA) chip. Therefore, the off-chip optical device is used to simulate the on-chip optical interconnection system to achieve the purpose of prototype verification. In this paper, based on the BEE4 development platform, the electrical interconnection is used for data communication on a single chip. The optical communication link is built by connecting Quad Small Form-factor Pluggable Plus (QSFP+) optical modules between Xilinx V6 series FPGA chips, and an optical communication network is constructed to realize the prototype of the optical hybrid interconnection network system. Taking the standard test sequence akiyo_qcif_176×144.yuv with resolution of 176×144 as an example, experimental results show that the optical link can replace the inter-chip electrical communication correctly, and the transmission time between boards is only half of electrical interconnection with integrated frequency of 51.327 MHz.
    FU Yi-wen, JIANG Lin, SHAN Rui, WU Hao-yue, Fan Meng. Implementation of Photoelectric Hybrid Interconnect Prototype System for Reconfigurable Video Array Processor[J]. Study On Optical Communications, 2020, 46(1): 17
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