To enhance the conversion speed of single-slope analog-to-digital converter (SS ADC) for low-noise CMOS image sensors, this study proposes a correlated multiple sampling (CMS) method based on SS ADC, which entails estimating the sampling time based on the input light intensity. Using the differential characteristic of the output signal of a digital-to-analog converter (DAC), the positive/negative ramp was selected according to input voltage. When the input voltage is low, the ramp shape was regulated such that there were four sampling times; when the input voltage is high, the sampling time was set to two. This design is based on 110-nm node CMOS process, and the clock frequency is 400 MHz, line conversion time is 23 μs, resolution is 11 bit, and quantization range is 1 V. The simulation results reveal that the differential nonlinearity (DNL) of this design is +0.6/-0.3LSB (LSB is least significant bit), and the integral nonlinearity (INL) is +0.7/-0.9LSB, with 82 μV being the minimum noise. Compared with conventional CMS method with sampling number of four, the A/D conversion time of the proposed method is saved by 13 μs without increasing noise under low light.