Linjie Zhou, Xinyi Wang, Liangjun Lu, Jianping Chen, "Integrated optical delay lines: a review and perspective [Invited]," Chin. Opt. Lett. 16, 101301 (2018)

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- Chinese Optics Letters
- Vol. 16, Issue 10, 101301 (2018)

Fig. 1. Data synchronization and buffering in optical networks.

Fig. 2. Photonics-assisted microwave beam forming and steering in phased array radar systems.

Fig. 3. Microwave photonic delay-line filter with a finite impulse response. PD, photodetector; VOA, variable optical attenuator; MUX, multiplexer; DEMUX, demultiplexer.

Fig. 4. Typical system configuration of optical coherence tomography.
![Four-channel pulse interleaver using WDM-TDM implemented on a silicon chip[27].](/Images/icon/loading.gif)
Fig. 5. Four-channel pulse interleaver using WDM-TDM implemented on a silicon chip[27].

Fig. 6. Three types of cascaded ring resonator delay lines: (a) SCISSOR; (b) CROW in transmission mode; (c) CROW in reflection mode.

Fig. 7. Four types of integrated BGs with periodic modulation of (a) waveguide height, (b) waveguide width, (c) slab width, and (d) cladding.
![(a) Standard grating waveguide and its delay spectrum. (b) Cascaded complementary apodized gratings[74].](/Images/icon/loading.gif)
Fig. 8. (a) Standard grating waveguide and its delay spectrum. (b) Cascaded complementary apodized gratings[74].
![BG delay line based on a 60-nm-thick silicon waveguide[35].](/Images/icon/loading.gif)
Fig. 9. BG delay line based on a 60-nm-thick silicon waveguide[35].
![ODLs based on (a) chirped BG[73] and (b) linearly chirped contra-directional couplers with uniform BG[80].](/Images/icon/loading.gif)
Fig. 10. ODLs based on (a) chirped BG[73] and (b) linearly chirped contra-directional couplers with uniform BG[80].

Fig. 11. ODL based on (a) line-defect PhCW and (b) coupled-cavity PhCW.

Fig. 12. Schematics of the switchable ODLs in (a) parallel and (b) serial configurations.

Fig. 13. 1 × N optical switches based on (a) cascaded 1 × 2 switch elements and (b) optical phased array.
![(a) Architecture of the continuously tunable ODL structure; (b) mask layout of the ODL chip[110].](/Images/icon/loading.gif)
Fig. 14. (a) Architecture of the continuously tunable ODL structure; (b) mask layout of the ODL chip[110].
![Recirculating loop delay line. (a) Integrated buffer; (b) gate matrix switch[113].](/Images/icon/loading.gif)
Fig. 15. Recirculating loop delay line. (a) Integrated buffer; (b) gate matrix switch[113].

Fig. 16. Recirculating loop delay line in a parallel switchable configuration.

Fig. 17. AWG-based wavelength-selective true-time-delay line. (a) Working principle illustration; (b) AWG layout.

Fig. 18. Implementation of an ODL based on frequency-to-time mapping.
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Table 1. Performance Comparison of Several Typical Integrated ODLs

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