III-V compound semiconductors，represented by InP，have recently emerged as a technology of choice for Tera-Hz（THz） applications due to their low noise，low power consumption and high gain performance^［1］. Northrop Grumman Space Technology first implemented the device withmaximum oscillation frequency（f_max）exceeding 1THz in 2007^［2］. In addition，their group successfully pushed the InP HEMT amplifier technology to 850 GHz for the first time in 2014^［3］. Currently，the record for current-gain cutoff frequency（f_T） is 750 GHz @ gate length（L_g） = 20 nm^［4］ and f_max is 1.5 THz @ L_g = 25 nm^［5］. Therefore，it is imperative to scale the physical gate length（L_g） to improve the frequency response of the device. However，the L_g cannot be reduced indefinitely. According to delay-time analysis^［6］，as the L_g decreases，the transit time under the gate $\tau$_text decreases sharply，resulting in a sharp increase in the proportion of extrinsic channel-charging delay $\tau$_text. Therefore，reducing $\tau$_text is another means to improve the device performance.

$\tau$_text is related to the parasitic resistance and parasitic capacitance. For the parasitic resistance，in addition to use multiple heavily doped cap layers^［7，8］，it is to reduce the width of the gate recess to minimize parasitic series resistances，such as the source and drain resistance（R_S and R_D）^［9］. The extrinsic capacitance can be decreased by increasing the spacing of gate recess or making a cavity structure^［10］.

The gate recess process is the most critical process for InP HEMTs manufacturing，which has a significant impact on parasitic series resistances and capacitance. Dae-Hyun Kim et al. studied the effects of the side-recess spacing（L_side），reporting that increasing L_side has a large impact on the subthreshold characteristics of the device due to a significant reduction of the gate leakage current and an improvement in its electrostatic integrity^［11］. Both M. Samnoun et al.^［12］ and Keisuke Shinoharal et al.^［13］ investigated the asymmetric gate recess technology，reporting that increase of the drain side recess（L_RD） improves the f_max due to the reduction of output conductance g_ds and capacitance C_gd. In addition，Tetsuya Suemitsu et al.^［14］ and Tae-Woo Kim et al.^［15］ developed a two-step-recessed gate process that improves high-speed performance.

However，seldom people have studied the impact of the asymmetric gate recess technology on two-step-recessed gate process. Therefore，it is imperative to carefully investigate the impact of the whole small recess offset in a double-recessed gate process on improving the high-frequency characteristics of InP HEMTs.

Table 1 shows the Gas Source Molecular Beam Epitaxy（GSMBE）-grown epitaxial layer structure on 3 inch semi-insulating InP（100） substrates that is used in this paper. In order to suppress the kink effect，the channel features a lattice-matched In_xGa_1-xAs with an indium content of 53%. In addition，a multi-layer cap structure that combines a heavily Si-doped multi-layer cap（In_0.65Ga_0.35As/In_0.53Ga_0.47As/ln_0.52Al_0.48As） were used to minimize a tunneling resistance associated with the barrier layer between the cap and channel layer. The concentration of Si-doping to a multi-layer cap is 3.0×10¹⁹，1.0×10¹⁹，and 1.0×10¹⁹ cm^-2 respectively. The 4-nm InP layer acts as an effective gate recess etch-stopper. Hall measurements were carried out at room temperature，showing the carrier mobility of over 10 000 cm²/（Vs） and the two-dimensional（2-DEG） sheet density of 3.26×10¹² cm^-2.

In order to avoid the degradation of the epitaxial structure by high temperature，the temperature of wafer in the whole fabrication process is lower than 300 ℃. Similar to our pervious work^［16］，mesa isolation is achieved by using multiple acids to successively etch the epitaxial layer to the buffer layer. After device isolation，source-drain metal electrodes are formed by Ti/Pt/Au（15 nm/15 nm/50 nm） with thermal annealing. The distance between source and drain electrode was designed to be 2.4 μm. The double-recessed gate process used to fabricate the T-shaped gates was as follows. Firstly，a SiO₂ thin film was deposited by plasma-enhanced chemical vapor deposition（PECVD） to improve adherence of photoresist. And the opening size of the SiO₂ mask was used to control the width of large gate recess. Next，the SiO₂ mask was etched by reactive ion etching（RIE） using CF₄ plasma after defining the gate-recess region by electronic beam lithography（EBL）. After RIE，the InGaAs cap layer was removed by a mix solution of citric acid（C₆H₈O₇） and hydrogen peroxide（H₂O₂） to form the large gate recess，where it was measured about 500 nm.

To abtain a small gate recess，a e-beam gate process was developed，which is shown in Table. 1. The PMMA/Al/UVIII e-beam stack layers were used to define the gate and small gate recess. In order to avoid the miscible of the two photoresist layers，the metal Al layer is used for isolation，and it is easily soluble in alkaline developer. The top UVIII resist was exposed by a small dose and wide line. After that，the gate head was determined by TMAH development and rinsed in DI water. Subsequently，the gate foot was defined on a single layer of PMMA resist and was exposed by a big dose and narrow line. The InAlAs cap layers were etched by H₃PO₄-solution down to the InP layer acting as an etch-stopped layer，where the small recess was measured about 100 nm. After the formation of the small recess，Ti/Pt/Au（3 nm/25 nm/350 nm） metals were evaporated and lifted off to form the T-shaped gate. The length of gate foot was 80 nm，and the gate stem was adjusted to be 250 nm to alleviate parasitic capacitances.

The whole small recess could be located at the large recess center，or with an offset toward source/drain，where the position of gate metals was in the middle of the small recess. The offsets from large recess center were 0.0 µm（type A），- 0.1 µm（type B），and + 0.1 µm（type C）.

Finally，these devices were covered with a 20-nm-thick Si₃N₄ dielectric film by PECVD（280 ℃）. The SEM image of the cross section of the fabricated device is shown in Fig. 1，which is the whole small recess toward source.

DC characteristics of devices were measured by an HP4142 semiconductor parameter analyzer. Figure 3（a） shows the typical output characteristics of the InP-based InGaAs/InAlAs HEMTs with 80-nm gate length and 50 μm × 2 gate width. These devices exhibit good pinchoff and excellent current saturation characteristics up to V_DS = 1.2 V. The type A device exhibits a better drain current driving capability（I_{D_max}）. These devices exhibit the almost same ON-resistance（R_ON），which is about 0.70 Ω·mm. This is because the ohmic contact and access resistance components are the same during the whole small recess offset. The drain and source resistances（R_D and R_S） are estimated from dc-measurements（R_S + R_D ≈ 0.546 Ω·mm），it can be also extracted from small signal equivalent circuit（SSEC） using a cold FET method ^［16］.

Figure 3（b） shows the measured transconductance（g_m） of the L_g = 80 nm devices as a function of I_DS at a drain bias of 0.8 V. As the I_DS increases，the g_m increases firstly up to the g_{m_max} and than decreases gradually. The type B device with the whole small recess toward source exhibits the largest g_{m_max}，which is 1105 mS/mm. The best characteristic arises from the smaller R_S.

Figure 4 shows the dependence of the DC drain conductance（g_{ds_dc}） on appiled V_DS. The V_GS takes the voltage value corresponding to the g_{m_max}. When V_DS increases，the g_{ds_dc} of these devices decreases sharply at first and then decreases slowly. When V_DS is greater than 0.6 V，the g_{ds_dc} of type C always keeps a trend of being less than that of type A and type B. Because g_{ds_dc} is obtained from ∂I_DS/∂V_DS and g_ds is obtained from Re（Y22） in the S-parameters，g_ds and g_{ds_dc} are related，which is consistent with the result of the parameters extraction below. From Equation（2），a smaller g_ds will contribute to improving the f_max.

The microwave characteristics of our representative L_g = 80 nm In_0.53Ga_0.47As/In_0.52Al_0.48As HEMTs are characterized from 0.1 to 50 GHz，using an Agilent precision network analyzer（PNA） system with off-wafer calibration. Pad parasitics are subtracted from the measured S-parameters using on-wafer OPEN and SHORT pads with identical geometry to the device pads. Figure 5 shows measured（symbols） and small-signal modeled（solid lines） H₂₁，MAG/MSG，and U versus frequency for these devices with the whole small recess offset. Using the de-embedded S-parameters，we build a conventional small-signal model，based on our previous research ^［17］. The bias condition is at V_DS = 0.8 V. And V_GS takes the voltage value corresponding to the g_{m_max}. From the de-embedded S-parameters，the values of f_T could be obtain by extrapolating H₂₁ with a slope of -20 dB/decade and the values of f_max are estimated from the small signal model. It is good that such a combination of f_T = 372 GHz and f_max = 394 GHz is demonstrated from the type C device with the whole small recess toward drain，at a relatively small value of V_DS = 0.8 V and V_GS = - 0.4 V.

Figure 6 plots the extracted f_T as a function of I_DS for these devices at V_DS = 0.8 V，which consists with the g_m against I_DS in Fig. 3（b）. The type C device have the largest f_T of all f_T - I_DS characteristics. At an I_DS of approximately 100 mA/mm which is a typical choice of the bias condition for most of the LNA designs，the type C device displays f_T over 275 GHz.

The f_T and f_max can be expressed as：

Table 2 shows the small-signal modeling parameters for different structures，including R_S，R_D，g_mi，C_gs，C_gd，and g_ds. Compared with type A and type B，type C has the smallest capacitance C_gs. This is because the type C device with the whole small recess toward drain results in smaller extrinsic capacitance. At the same time，according to Table 2 and Fig. 4 shows that the type C has the smallest g_ds. Although the g_mi of type C is the smallest，the parasitic resistance of the three devices is almost the same，and combined with the influence of other parameters，the type C finally obtains the largest f_T. In terms of f_max，it depends on the combined infulence of several parameters. The type C device obtains the largest f_max due to the small g_ds and large f_T. Therefore，it should be finally emphasized that the device with the whole small recess toward drain in a double-recessed gate process could improve the high-frequency characteristics.

In summary，we experimentally investigate the impact of the whole small recess offset on the lattice-matched InP-based HEMTs in a double-recessed gate process，where L_g = 80 nm. These devices exhibit the same R_ON，and the device with the whole small recess toward source has the largest g_{m_max} due to a smaller R_s. For RF responses of these devices，the device with the whole small recess toward drain achieves an excellent characteristic of f_T = 372 GHz，and f_max= 394 GHz. In the following research，the g_m of the device will be further improved to increase the f_T by using a channel with Indium-rich composition.

This work was supported by Development of Terahertz Multi-user RF Transceiver System（Grant No. Z211100004421012）. The authors would like to thank Yan-kui Li for his assistance during the measurements. We thank Engineer Feng Yang for his discussion on the process and Professor Ding Peng for his guidance.