With the continuous evolution of interconnection networks, the exponential growth of data center (DC) traffic has posed a significant challenge to communication systems. In addition, remarkable advancements have been achieved in both DCs and high-performance computing (HPC) over the past decade. As Moore’s law reaches its limitations, traditional electronic-based networks have begun to exhibit drawbacks in terms of speed, power consumption, latency, and capacity. Optical interconnects are thus emerging as an effective solution for high-density, high-speed data transmission^[1–3]. In this context, silicon photonics has gained significant attention thanks to its mature standard semiconductor fabrication process, leveraging the existing and well-established complementary metal-oxide semiconductor (CMOS) manufacturing technology^[4]. Based on silicon-photonic (SiPh) platforms, optoelectronic interconnections with low latency, high integration, high bandwidth, and low power consumption have been widely proposed^[5–7].

To further increase the communication rate of the overall system, it is common practice to employ the wavelength division multiplexing (WDM) technique^[8–10] and advanced modulation formats^[11–13]. When considering this scenario, it is imperative to prioritize the performance of the SiPh devices, which is intricately linked to the design and fabrication process. This implies an in-depth optimization of the electrode structure, doping strategy, germanium (Ge) morphology, and epitaxy process of the photodetector (PD)^[14,15]. Additionally, the parasitic parameters of the optoelectronic interconnection and the architecture of the transimpedance amplifier (TIA) chips are also pivotal^[16,17]. This necessitates co-simulating electrical integration circuits (EICs) and photonic integration circuits (PICs) to inform the co-packaged optics (CPO) layout in the multichannel receiver module, ultimately expanding the bandwidth of the integrated system while mitigating channel cross talk at high frequencies^[18–28]. To achieve this, an equivalent circuit model of the PD and the package parasitic is constructed. This approach easily establishes a whole optoelectronic simulation system for photonic and electrical devices.

In this paper, we present a $4\times 112\mathrm{Gb}/\mathrm{s}$ hybrid integrated silicon receiver that consists of a four-channel vertical p-i-n PD array and a four-channel TIA. Each channel operates at a data rate of 112 Gb/s using four-level pulse amplitude modulation (PAM-4). Additionally, we employ electro-optical co-simulation^[23,24] to guide the design and co-packaging of optoelectronic devices. To begin, we design and fabricate a high-speed SiPh p-i-n PD with a 3-dB bandwidth of 36 GHz. Then, we construct an equivalent circuit model of the PD and package parasitic, enabling the TIA to enhance system performance at high frequencies with the aid of a continuous-time linear equalization (CTLE) circuit and shunt peaking. The optical-to-electrical (O-E) 3-dB bandwidth of the proposed receiver is measured to be 48 GHz. Clear eye diagrams up to 112 Gb/s in PAM-4 are observed with a bit error rate (BER) below the forward error correction (FEC) threshold of 2.4 × 10⁻⁴ (KP4-FEC) and a power consumption of 2.2 pJ/bit.

In this section, we will discuss the entire design process based on electro-optical co-simulation. The architecture diagram of the proposed receiver is shown in Fig. 1(a) with two parts. The optical part mainly consists of a high-speed PD, which receives the optical signal and converts it to the photocurrent. The electrical part is a high-speed TIA, which performs equalization and amplification on the electrical signal. Therefore, an end-to-end equivalent circuit model including the package parasitic characteristics of the wire-bonding can be established to optimize system performance.

The vertical p-i-n PD utilized in the optical receiver is fabricated on a high-resistance silicon-on-insulator (SOI) platform; the device model is presented in Figs. 1(b) and 1(c). The material selected for the photon absorption layer is germanium (Ge), as the epitaxial growth process of Ge-on-Si is relatively mature and offers significant advantages in terms of high electron/hole mobility and a high absorption coefficient. Typically, three crucial parameters are used to evaluate the device performance: bandwidth, responsivity, and dark current, which are influenced by the size of the Ge region. Due to the design rule constraints of the foundry, it is recommended that the height and width of the Ge layer remain fixed. As a result, the responsivity and dark current of the PD will increase with an increase in Ge length, while the RC-limited bandwidth will decrease for a higher junction capacitance of the p-i-n PD^[14]. Therefore, there exists a certain trade-off between bandwidth and responsivity.

For the PD device simulation in this work, we assume that the quantum efficiency of the Ge material is 100%, representing an ideal condition. However, the device parameters cannot be perfectly simulated due to crystal defects in Ge and the Ge–Si interface during the heteroepitaxial growth process, which are inherently unpredictable. Since the dark current mainly depends on the fabrication process and the material defect distribution, we calculate the trends of the bandwidth and responsivity varying with the Ge length, as shown in Fig. 2(a). It is evident that a long Ge layer allows for better photon absorption, but results in frequency response degradation. A length of 20 µm is chosen to prioritize the high responsivity requirement of the PD, and the bandwidth can be compensated through the bandwidth extension technique of TIA at the system level, as mentioned later. The frequency response of the PD is calculated in Fig. 2(b), with a 3-dB bandwidth above 43 GHz and a responsivity above 1 A/W under a 2 V bias voltage. The electrical field from the side view at the middle width of the Ge area is presented in the Fig. 2(b) inset, indicating that the photons are almost entirely absorbed within 20 µm.

The architecture of the TIA utilized in this optical receiver is presented in Fig. 1(a), and it consists of two components in a single channel: high-speed modules and direct-current (DC) modules. The high-speed modules include a $\mathrm{T}\text{-}\mathrm{\pi }$ type bandwidth expansion module, an input transimpedance stage (TIS), a variable gain amplifier (VGA), a main amplifier (MA), and an output buffer (BUF). The $\mathrm{T}\text{-}\mathrm{\pi }$ type bandwidth expansion module that consists of artificial on-chip inductance, bonding wire inductance, and numerous parasitic capacitances is designed to form a two-order series peaking^[29], which surpasses bandwidth limitations and enhances high-speed impedance matching. The faint current signal from the PD is amplified and transformed into a voltage signal by the low-noise TIS, which is implemented in a shunt-feedback topology. With the topology of current steering, the differential VGA provides programmable gain, refraining from nonlinearity when the input signal is large, while the MA amplifies the signal to the required amplitude. The output buffer is matched to a 50 Ω resistive load and provides an output voltage swing up to 0.6V_pp, sufficient to drive subsequent circuits such as analog-to-digital converters (ADCs) or digital signal processors (DSPs). DC modules are employed to guarantee suitable DC operating points. A received signal strength indicator (RSSI) module in a low dropout (LDO) regulator structure is applied to achieve constant PD supply and therefore realize constant bias voltage for PD with a fixed input DC operating point. Additionally, the DC offset cancellation module is activated in VGA and BUF to ensure differential operation.

In the electro-optical co-simulation, the SiPh device and package parasitic are converted into an equivalent circuit, as shown in Fig. 3(a). Specifically, $I_{\mathrm{pd}}$ represents the current generated from the p-i-n PD after photon absorption, while $C_j$ and $R_j$ represent the equivalent capacitance and resistance of the PN junction. Typically, the p-i-n PD operates under reverse bias, so $R_j$ is large enough to be neglected. Additionally, parameters $C_{\mathrm{ox}}$, $R_{\mathrm{ox}}$, and $C_{\text{pad-}\mathrm{PD}}$ describe the substrate capacitance, substrate resistance, and capacitance of the pads. The L_s represents on-chip series inductance, and the $C_{\mathrm{TIA}}$ represents the equivalent input capacitance of TIA. The values for $C_j$, $R_s$, $C_{\mathrm{ox}}$, and $R_{\mathrm{ox}}$ are extracted from the simulated S-parameter of the PD in Fig. 2(b), which are 50 fF, 20 Ω, 8 fF, and 8000 Ω. The parasitic parameters of the pads and wire bonding are $C_{\text{pad-}\mathrm{PD}}$, $C_{\mathrm{pad}-\mathrm{TIA}}$, and $L_{\mathrm{wb}}$. As a main component of the $\mathrm{T}\text{-}\mathrm{\pi }$ network, the inductor induced by the wire bond impacts the frequency response in a mechanism known as series peaking, which is able to extend the bandwidth but introduces unwanted peaks in the S21 curve^[29]. Therefore, optimization of the wire bond inductance, as shown in Fig. 3(b), is considered to balance the trade-off between high bandwidth and flat transimpedance. A large bandwidth extension with a flat S21 response is achieved with an optimal inductance of 150–250 pH. To achieve such a low value, the printed circuit board (PCB) is customized with a groove for thick photonic chips, as shown in Fig. 3(c). This maintains a uniform surface height between the PICs and EICs while lowering the wire bond length and inductance. In addition, we adopt the double-wire bonding, which can effectively reduce transmission loss and enhance connectivity. Through this approach, the inductance introduced by wire bonding is easily lowered to the optimal range.

The frequency response from the co-simulation is presented in Fig. 3(d). Compared to the 43 GHz bandwidth of the PD, with the equalization provided by the TIA, the simulated 3-dB bandwidth of the receiver is extended to over 50 GHz, as indicated by the solid blue line. Multiple bandwidth expansion technologies, including CTLE and shunt peaking, are widely employed in TIA design to compensate for the high-frequency portion of the S21 curve and induce a wave peak that can widen the 3-dB bandwidth of the optoelectronic system. By adjusting the degeneration resistor and capacitor in VGA, MA, and BUF, the peaking effect can be further enhanced, as indicated by the dashed blue line. However, an excessively large peak can result in a mismatch of the group delay at different frequencies, leading to signal distortion, as shown in Figs. 3(e) and 3(f). For the overall receiver system, a flattened S21 curve in the co-simulation is preferred. Additionally, an optimized gain distribution in the TIA circuit is considered to match the linear output swing range of each stage. The gain of the VGA stage can be adjusted over a wide range, reducing nonlinearity issues stemming from a large input signal from the PD.

After completing the device simulation and layout drawing, the chip fabrication and testing were carried out. The proposed PD was designed and fabricated using a 180 nm silicon photonics platform, while the TIA was fabricated on a 180 nm SiGe BiCMOS platform. The chips occupied areas of $1.4\mathrm{mm}\times 3.2\mathrm{mm}$ and $1.1\mathrm{mm}\times 3.2\mathrm{mm}$, respectively. The micrographs of the chips and the proposed optical receiver after co-packaging are shown in Figs. 4(a) and 4(b). For a multichannel module, cross talk is a crucial consideration, which mainly originates from the TIA array. Much effort is made in design to overcome this issue, including placing a high-speed pathway in the middle of the channels and protecting the transmission lines with ground shielding and a dummy. After that, the four-channel PD and TIA were mounted on a high-speed circuit board and connected using 25 µm diameter gold wire, as shown in Fig. 4(a). Following the co-packaging process shown in Fig. 4(b), with a fiber array, four end-launches, and a thermoelectric cooler (TEC), the receiver achieved higher stability, as the probe and optical fiber testing were eliminated.

The measurement setup, shown in Fig. 4(c), was adopted to characterize the output eye diagrams. The Keysight arbitrary waveform generator (AWG) produced digital electrical signals at different data rates, which were then amplified by the RF linear amplifier and transmitted to a commercial Mach–Zehnder modulator (MZM). This device modulated the continuous wave (CW) light into intensity-modulated light. The variable optical attenuator was used to adjust the optical power entering the device under test (DUT) to prevent potential damage to the PD and ensure that the system operated within a linear region. The polarization controllers (PCs) adjusted the polarization states of the light to meet the specific requirements of silicon photonics devices, such as MZMs and couplers, which are highly sensitive to polarization. A variable optical attenuator (VOA) was employed to prevent the potential damage resulting from excessive power. The modulated light was received by the proposed receiver and converted into a modulated electrical signal. Finally, the Keysight digital sampling oscilloscope captured the signals and displayed the eye diagrams.

First, a high-speed vector network analyzer is utilized to measure the O-E S-parameters of the receiver and the PD. As shown in Fig. 5(a), the frequency response results are normalized, and the 3-dB O-E bandwidth of the PD is above 36 GHz. Owing to the uncontrollable sealing process, the parasitic capacitor and bonding wire are smaller and longer than expected, respectively. Therefore, the flatness of S21 around 40 GHz is partially damaged. However, later measurement of the eye diagram shows that this is acceptable for data rates up to 112 Gb/s. After the bandwidth compensation and equalization by TIA, the O-E bandwidth of the whole system is improved to 48 GHz. This improvement can be attributed to the peaking inductors of TIA. By adjusting the equalizer, we can flatten the S21 curve. However, when adjusting the equalizer setting or gain of TIA, it is crucial to consider the clarity of the eye diagrams to achieve the best signal transmission quality. The S21 curves for all four channels are presented in Fig. 5(a) with similar 3-dB bandwidth, demonstrating good consistency between channels. Figure 5(b) illustrates the results of the PD measurement, including the current and responsivity. Under reverse bias, the PD exhibits a normal PN-junction characteristic. The average dark current is smaller than 10 nA at –2 V, as shown by the red curve. With an optical power of approximately 0-dBm incident, the photocurrent increases to 0.95 mA, resulting in a measured responsivity of approximately 0.96 A/W. When the reverse bias voltage rises, the responsivity and the light current rapidly increase to a stable value. Compared to the simulated results, the measured data exhibit lower bandwidth, lower responsivity, and worse peaking flatness. This difference can be attributed to the nonuniform doping density of silicon and crystal defects in the epitaxial Ge material. Additionally, during the wire-bonding process, the length of the golden wires is slightly larger than that in the simulation, inducing a higher bandwidth and worse flatness. This causes group delay mismatch and nonlinearity in eye diagrams. To further improve the receiver performance, iterations of the design can be conducted.

The eye diagram testing setup is shown in Fig. 4(c). The AWG and oscilloscope are used to generate and receive digital signals, respectively. After the calibration, the losses from devices other than the DUT have been de-embedded. Figures 6(a) and 6(b) display the optical eye diagrams output from the MZM before entering the DUT. Pseudo-random binary sequence (PRBS) pattern data with a length of 2⁷−1 are applied, and the average optical power is $-3\mathrm{dBm}$. Figures 6(c), 6(d), and 6(e) show the measured eye diagrams at 56 Gb/s NRZ, 80 Gb/s PAM-4, and 112 Gb/s PAM-4. Comparing Figs. 6(a) and 6(b) with Figs. 6(c) and 6(d), it can be observed that the proposed receiver exhibits good linearity, as the electrical eye diagrams faithfully mirror the shape of the optical eye diagrams, albeit with the inclusion of additional noise. Figures 6(e)–6(h) show eye diagrams at 112 Gb/s PAM-4 for different channels, demonstrating good consistency in device performance. The measured level separation mismatch ratios ($R_{\mathrm{LM}}$) for the four channels are 0.919, 0.955, 0.925, and 0.934, respectively. All eye diagrams are measured without the aid of the TDECQ equalizer in the oscilloscope. The results present clear and opening eyes with good linearity. The slight tilt and asymmetry observed in the 112 Gb/s PAM-4 eye diagrams are attributed to excessive peaking and group delay mismatch.

To explore the sensitivity of the proposed optical receiver, the transmission BER is measured, while the optical input power of the PD is tuned through the VOA. The BER results with different input optical powers at 56 GBaud are shown in Fig. 7(a). The BER performances as a function of input power for 56 GBaud signal reception are obtained. For 112 Gb/s in PAM-4, the BER easily achieves the KP4-FEC threshold (2.4 E-4) under the input optical power of $-4\mathrm{dBm}$, which implied the error-free state can be realized after FEC. Additionally, the BER in NRZ modulation achieves 1 × 10⁻¹² (error-free) at a power level of $-4\mathrm{dBm}$, indicating that there are almost no errors in this case. Linearity of the O-E receiver is considered in form of total harmonic distortion (THD) measurement, as shown in Fig. 7(b). Since the PD outputs a faint current signal and can hardly suffer from nonlinearity, its THD is ignored to simplify the measurement setup. Therefore, the EIC’s THD with an electric input is tested and regarded as an overall THD behavior of the receiver. With input signal set at 1 GHz and 10 harmonics considered, THD is guaranteed to be less than 5% at an input of 1 mA. By reducing the gain provided by the VGA, it could be further improved, indicating potential to receive an ultralarge input current.

The characteristics of the representative SiPh receivers are summarized in Table 1. Compared to the state-of-the-art SiPh receivers, the optical receiver proposed in this work exhibits a large 3-dB bandwidth, high data rates, and a power consumption of 2.2 pJ/bit. The power consumption is calculated by summing the total power provided to the TIA, encompassing all channels and modules. The TEC is not required when operating at room temperature. The 180 nm process technology also shows cost advantages in fabrication. Additionally, it does not require the TDECQ equalizer or any filters from oscilloscopes. With the potential to present clear and open eye diagrams for 128 Gb/s PAM-4 or even higher data rates, the receiver’s performance can be further enhanced with equalizer modules and larger bandwidth test equipment.

We have demonstrated an optimized 400G optical receiver that is integrated by SiPh and SiGe BiCMOS technology designed through an electro-optical co-simulation method. An equivalent circuit model was established to optimize the performance of the integration system. After fabrication and co-packaging, the 3-dB O-E bandwidth was improved to over 48 GHz, compared to 36 GHz for a single PD. Without the need for a TDECQ equalizer or any filters from oscilloscopes, clear and open eye diagrams were observed under 56 Gb/s NRZ and 112 Gb/s PAM-4 modulation. Additionally, BER measurements demonstrate a sensitivity of $-4\mathrm{dBm}$ at the KP4-FEC threshold for 112 Gb/s PAM-4, with a power consumption of only 2.2 pJ/bit. This work on a silicon receiver highlights the immense potential of high-speed optical communication and high-performance optical computing.