For thermal imaging，the cryogenic mid-wave infrared（MWIR）imager has high contrast and resolution ^［1］，so MWIR is widely applied in astronomy，security and surveillance applications. The infrared focal plane array（IRFPA）is the critical component of the infrared imager，consisting of an infrared detector array and a readout integrated circuit（ROIC）. To avoid inducing thermal interference in the infrared detector and deteriorating the efficiency and lifetime of the refrigeration machine，low power consumption is critical for cryogenic IRFPAs ^［2-3］.

Because of the short analog signal chain and the data transmission in digital domain，digital ROIC（DROIC）with on-chip analog-to-digital converter（ADC）has been developed and has the advantages of superior signal-to-noise ratio（SNR）and anti-interference capacity ^［4］. Generally，there are three main kinds of on-chip ADCs：chip-level，column-level and pixel-level，and the latter two kinds are the focus of research ^［5-7］. In Ref.［5］，a column-level dual ramp ADC is presented for high resolution and short conversion time. However，because the conversion time of column-level ADC equals the row period，column-level ADC is limited by the tradeoff between conversion time and power consumption with the increase of the array size and the frame rate like chip-level ADC. Pixel-level ADC has shorter analog signal chain and operates at the frame rate，so it has low-bandwidth and low-noise potential ^［3］. In Ref.［6］，a pixel-level pulse-frequency-modulation（PFM）ADC with extended-counting circuit is reported for large charge-handling capacity and is widely used in long-wave infrared imagers. In Ref.［7］，a pixel-level single-slope（SS）ADC is described and is suitable for MWIR imagers. In these implementations，although the bandwidth requirement is low，the pixel-level comparator is always on，leading to high average power.

In this paper，a low-power DROIC with 15-bit pixel-level SS-ADC for MWIR imagers is proposed. A power-self-adaptive pulse comparator is presented to address the challenge of power consumption for the pixel-level ADC. Only when the ramp signal approaches the voltage on the integration capacitor，there is current flowing through the comparator. In addition，compared with the conventional step output，its pulse output makes 15-bit pixel memories store analog-to-digital（A/D）conversion results only once and the dynamic power consumed on the memories is reduced. The memories adopt a 3-transistor（3T）dynamic structure and only occupy 54 $\mathrm{\mu }{\mathrm{m}}^{\mathrm{2}}$，meeting the area limitation of small pixel pitch. The data retention capability of the dynamic memories is not a concern at liquid nitrogen temperature ^［8］. Besides，there is large parasitic capacitance on column data buses，so a global gray-coded counter，whose values are applied to the column buses，is adopted for low dynamic power consumption. Because there is only one different bit between two successive gray codes，the jump times are reduced and the error rate is low. After A/D conversion，the data in pixel memories are read out to column in current mode to avoid voltage crosstalk between adjacent bus lines.

The structure of this paper is as follows. Section 1 introduces the proposed readout circuit and its operating principle. The pixel-level power-self-adaptive pulse comparator，pixel-level dynamic memory and column data write/read circuit are detailed. Section 2 presents the experimental results. The conclusion is given in Sect. 3.

A low-power DROIC for MWIR imagers with the pixel-level SS-ADC is proposed. The DROIC adopts direct injection（DI）structure to meet the restricted area limitation of pixels with ADC ^［9］. The current injection efficiency $\eta$，which is defined as the ratio of the current $I_{\mathrm{I}\mathrm{N}}$ flowing into ROIC to the detector photocurrent $I_{\mathrm{D}}$，is calculated by Eq. 1 where $g_{\mathrm{m}}$ is the transconductance of the injection transistor and $R_{\mathrm{D}}$ is the infrared photon detector resistance ^［1］. In MWIR applications，$R_{\mathrm{D}}$ is generally large，so $\eta$ is high enough and it is appropriate to adopt the DI structure.

where $I_{\mathrm{I}\mathrm{N}}$ is integrated on the capacitor $C_{\mathrm{I}\mathrm{N}\mathrm{T}}$ and is converted to the voltage $V_{\mathrm{I}\mathrm{N}\mathrm{T}}$ which is then digitalized. The SS-ADC is an appropriate architecture for pixel-level ADCs due to its compact feature ^［10］. The ramp generator and the counter are shared by all pixels. Only a comparator and N-bit memories are located in the pixel. The simplified block diagram of the conventional digital pixel with SS-ADC ^［7，10］ is shown in Fig. 1. After integration，$V_{\mathrm{I}\mathrm{N}\mathrm{T}}$ and the ramp bus signal $V_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}}$ are connected to the inputs of the pixel comparator. The data in pixel memories are continuously refreshed following the counter bus signals $BUS<N:\mathrm{1}>$ before the output of the comparator $WRT<i,j>$ flips. When $WRT<i,j>$ flips，$BUS<N:\mathrm{1}>$ are latched as A/D conversion results. In such structure，the comparator needs to operate at low-noise and high-speed mode throughout the A/D conversion process to meet the requirements of SNR and linearity ^［10］. In addition，column driver circuit consumes much power to refresh the data of pixel memories.

Figure 2 illustrates the block diagram of the proposed digital pixel with 15-bit SS-ADC and the proposed low-power DROIC based on this digital pixel. A novel power-self-adaptive pulse comparator is presented and a sampling capacitor $C_{\mathrm{S}}$ is added. $C_{\mathrm{M}\mathrm{O}\mathrm{S}}$ and $C_{\mathrm{S}}$ are MOS and MIM capacitors respectively and are both used as integration capacitors during the integration phase to increase the charge handling capacity in the compact pixel. The total integration capacitor $C_{\mathrm{I}\mathrm{N}\mathrm{T}}$ equals $C_{\mathrm{M}\mathrm{O}\mathrm{S}}+C_{\mathrm{S}}$.

The timing diagram of the proposed DROIC is shown in Fig. 3. ${\varphi }_{\mathrm{I}\mathrm{N}\mathrm{T}}^{\text{'}}$ is the delay signal of ${\varphi }_{\mathrm{I}\mathrm{N}\mathrm{T}}$. After the integration phase when the detector current is integrated on $C_{\mathrm{M}\mathrm{O}\mathrm{S}}$ and $C_{\mathrm{S}}$，the signal ${\varphi }_{\mathrm{A}\mathrm{D}}$ is on and the voltage on $C_{\mathrm{S}}$ is quantized by the pixel SS-ADC. Though the switch controlled by ${\varphi }_{\mathrm{I}\mathrm{N}\mathrm{T}}^{\text{'}}$ injects charge to $C_{\mathrm{S}}$，its gate capacitor is far less than $C_{\mathrm{S}}$ so that the linearity of this ADC is scarcely affected. During the A/D phase，the ramp signal $V_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}}$ is connected to the left plate of $C_{\mathrm{S}}$ and its corresponding gray-coded bus signals $BUS<\mathrm{15}:\mathrm{1}>$ are connected to the 15-bit dynamic memories. $BUS<\mathrm{15}:\mathrm{1}>$ are driven by the column data write/read（W/R）circuit. Owing to the bottom-plate-sampling technique，when $V_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}}=V_{\mathrm{I}\mathrm{N}\mathrm{T}}$，the negative input voltage of the comparator $V_{\mathrm{N}}$ equals the reference voltage $V_{\mathrm{R}\mathrm{E}\mathrm{F}}$. Once $V_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}}<V_{\mathrm{I}\mathrm{N}\mathrm{T}}$，the digital codes of $BUS<\mathrm{15}:\mathrm{1}>$ are written into the pixel memories by the narrow pulse output of the comparator $WRT<i,j>$. During the pixel-to-column readout（RO）phase，the data in the pixel memories are read out to column memory array via $BUS<\mathrm{15}:\mathrm{1}>$ by the column data W/R circuit row-by-row. In the next frame，the data in the column memory array are output off the DROIC through the data output multiplexer（MUX）circuit.

This proposed DROIC achieves low-power performance in the compact pixel due to several adopted techniques，which are detailed in Sect. 1.2 and 1.3，including the power self-adaptive pulse comparator and the gray-coded bus signals.

The proposed low-power pixel-level power-self-adaptive pulse comparator is shown in Fig. 4（a）together with other pixel circuits drawn as dotted lines. Some signals correspond to the counterparts in Fig. 2. The comparator consumes ultra-low average power with low-noise and high-speed performance to meet the SNR and linearity requirements of DROIC.

$V_{\mathrm{R}\mathrm{E}\mathrm{F}}$ is set to Eq. 2. $V_{\mathrm{T}\mathrm{H}\mathrm{P}}$ is the threshold voltage of PMOS transistors. $V_{\mathrm{O}\mathrm{V}\mathrm{2}}$ and $V_{\mathrm{O}\mathrm{V}\mathrm{5}}$ are the overdrive voltages of $M_{\mathrm{2}}$ and $M_{\mathrm{5}}$ when their drain currents are $I_{\mathrm{0}}/\mathrm{2}$ and $I_{\mathrm{0}}$，respectively. $I_{\mathrm{0}}$ is the saturation current of $M_{\mathrm{5}}$ when the gate voltage $V_{\mathrm{G}\mathrm{5}}$ of $M_{\mathrm{5}}$ equals $V_{\mathrm{B}\mathrm{P}}$. $∆V$ is about 50 mV to ensure $M_{\mathrm{1}}$ and $M_{\mathrm{2}}$ in saturation region when $V_{\mathrm{N}}=V_{\mathrm{R}\mathrm{E}\mathrm{F}}$.$M_{\mathrm{8}}$ is biased by $V_{\mathrm{S}\mathrm{S}}$ to match $M_{\mathrm{7}}$. $M_{\mathrm{6}}$ is biased by $V_{\mathrm{B}\mathrm{P}}$ to limit the short current of the comparator’s second stage when $\left|V_{\mathrm{N}}-V_{\mathrm{R}\mathrm{E}\mathrm{F}}\right|$ is small.

The timing diagram of the comparator is depicted in Fig. 4（b）. The comparator works as follows. During the integration phase，$V_{\mathrm{G}\mathrm{5}}=V_{\mathrm{D}\mathrm{D}}$，$V_{\mathrm{N}}=V_{\mathrm{R}\mathrm{E}\mathrm{F}}$，$R_{\mathrm{C}\mathrm{M}\mathrm{P}}$ and $\overline{{\varphi }_{\mathrm{A}\mathrm{D}}}$ are ‘1’. Therefore，the total current of the comparator $I_{\mathrm{C}}$ is zero and $WRT<i,j>$ is ‘0’. The RS-latch consisting of two NOR gates is reset by the signal $R_{\mathrm{C}\mathrm{M}\mathrm{P}}$.

During the A/D conversion phase，$V_{\mathrm{G}\mathrm{5}}=V_{\mathrm{B}\mathrm{P}}$，$\overline{{\varphi }_{\mathrm{A}\mathrm{D}}}$ and $R_{\mathrm{C}\mathrm{M}\mathrm{P}}$ are ‘0’. $M_{\mathrm{5}}$ is turned on. $V_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}}$ is initially equal to a high voltage so that $V_{\mathrm{N}}$ becomes higher than $V_{\mathrm{R}\mathrm{E}\mathrm{F}}$ and falls with the decline of $V_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}}$. $V_{\mathrm{N}}$ is expressed as：

（I）When $V_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}}\ge V_{\mathrm{I}\mathrm{N}\mathrm{T}}+\left|V_{\mathrm{O}\mathrm{V}\mathrm{2}}\right|+\left|V_{\mathrm{O}\mathrm{V}\mathrm{5}}\right|+∆V$，$V_{\mathrm{N}}\ge V_{\mathrm{D}\mathrm{D}}-\left|V_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|$ so that $M_{\mathrm{1}}$ is in cut-off region. Due to the current mirror consisting of $M_{\mathrm{3}}$ and $M_{\mathrm{4}}$，$M_{\mathrm{4}}$ is also in cut-off region. As a result，the node $V_{\mathrm{M}\mathrm{I}\mathrm{D}}$ equals ‘1’ and $WRT<i,j>$ equals ‘0’. Within this range，$I_C$ is zero，namely the comparator has no power consumption.

（II）When $V_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}}$ falls below $V_{\mathrm{I}\mathrm{N}\mathrm{T}}+\left|V_{\mathrm{O}\mathrm{V}\mathrm{2}}\right|+\left|V_{\mathrm{O}\mathrm{V}\mathrm{5}}\right|+∆V$，but is higher than $V_{\mathrm{I}\mathrm{N}\mathrm{T}}$，$I_{\mathrm{C}}$ increases from zero and $WRT<i,j>$ is still ‘0’.

（III）When $V_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}}$ is just below $V_{\mathrm{I}\mathrm{N}\mathrm{T}}$，$WRT<i,j>$ becomes ‘1’. $V_{\mathrm{G}\mathrm{7}}$ is set to ‘1’，which induces $M_{\mathrm{7}}$ into the cut-off region. The gray-coded bus signals on $BUS<\mathrm{15}:\mathrm{1}>$ of this moment are latched in pixel dynamic memories. As in case（I），$I_{\mathrm{C}}$ changes back to zero，and $WRT<i,j>$ becomes ‘0’. This state remains until the A/D conversion ends.

$I_{\mathrm{5}}$ and $I_{\mathrm{6}}$，which are the drain current of the transistors $M_{\mathrm{5}}$ and $M_{\mathrm{6}}$，are illustrated in Fig. 4（b）. $I_{\mathrm{C}}\approx I_{\mathrm{5}}+I_{\mathrm{6}}$. $I_{\mathrm{5}}$ is the largest proportion of $I_{\mathrm{C}}$. Figure 5 shows the simulation results of $I_{\mathrm{C}}$ when $V_{\mathrm{I}\mathrm{N}\mathrm{T}}$ equals 0.8 V and 1.5 V，respectively. It demonstrates that there is current flowing through the comparator only when $V_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}}$ approaches $V_{\mathrm{I}\mathrm{N}\mathrm{T}}$，namely $V_{\mathrm{N}}$ approaches $V_{\mathrm{R}\mathrm{E}\mathrm{F}}$. The average value of $I_{\mathrm{5}}$ is less than 20% of $I_{\mathrm{5}}$’s maximum value which equals to the average value of the traditional comparator with the same performance.

In summary，the voltage range $∆V_{\mathrm{I}}$ of $V_{\mathrm{N}}$，where $I_{\mathrm{5}}>\mathrm{0}$，is given by Eq. 4 and is much smaller than the voltage swing $∆V_{\mathrm{S}\mathrm{W}}$ of $V_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}}$. The comparator’s average power consumption $P_{\mathrm{C}\mathrm{M}\mathrm{P}}$ can be calculated by Eq. 5. $T_{\mathrm{F}}$ and $T_{\mathrm{A}\mathrm{D}}$ are the frame time and the A/D conversion time，respectively. Because $T_{\mathrm{A}\mathrm{D}}\ll T_{\mathrm{F}}$ and $∆V_{\mathrm{I}}+∆V\ll ∆V_{\mathrm{S}\mathrm{W}}$，$P_{\mathrm{C}\mathrm{M}\mathrm{P}}$ is very low and is far less than the counterpart of always-on comparator. Cooperating with the DROIC operation principle that $V_{\mathrm{N}}$ equals $V_{\mathrm{R}\mathrm{E}\mathrm{F}}$ when the comparator flips，high SNR and high speed are realized under ultra-low average power consumption.

During the A/D conversion phase，the bus signals on $BUS<\mathrm{15}:\mathrm{1}>$ are latched in pixel-level memories controlled by the pixel comparator’s pulse output. The smaller area the memories occupy，the larger the charge handling capacity is. Noting that the leakage current is extremely low at liquid nitrogen temperature ^［8］，a 3T dynamic memories with a single write/read port is implemented to store the A/D conversion results and its data retention capability is not a concern. Besides，the 15-bit column bus lines are placed in the small-width column，so there is large parasitic capacitance（>1pF）and voltage crosstalk between adjacent bus lines. The bus signals are generated from a global gray-coded counter to reduce the jump times for lower dynamic power consumed on the column buses. A column current comparator is adopted to read out the data from pixel memories to column memory array for robustness against voltage crosstalk between adjacent bus lines.

The circuit diagram of the pixel dynamic memories and the column data W/R circuit，which consists of tri-state gates and current comparators，is shown in Fig. 6.$\overline{{\varphi }_{\mathrm{C}}}$ and ${\varphi }_{\mathrm{C}}$ are complementary signals.

During the A/D conversion phase，the global gray-coded counter starts from zero and the tri-state gates are enabled by the enable signal $E{N}_{\mathrm{T}\mathrm{R}\mathrm{I}}$. The counter results $G<\mathrm{15}:\mathrm{1}>$ are transmitted to $BUS<\mathrm{15}:\mathrm{1}>$. When $WRT<i,j>$ in the pixel of the ${\mathrm{i}}^{\mathrm{t}\mathrm{h}}$ row and the ${\mathrm{j}}^{\mathrm{t}\mathrm{h}}$ column flips，the bus signals on $BUS<\mathrm{15}:\mathrm{1}>$ are written in the memories. In the meantime，the column comparator is in the sleep mode.

During row-by-row pixel-to-column readout phase，${\varphi }_C$ is ‘1’. The current comparators are powered on and are connected to $BUS<\mathrm{15}:\mathrm{1}>$. The readout signal $RD<\mathrm{i}>$ controls the A/D conversion results’ readout. If the pixel memory stores ‘0’，no current flows into this memory so that the drain current $I_{\mathrm{2}}$ of $M_{\mathrm{2}}$ is equal to the drain current $I_{\mathrm{1}}$ of $M_{\mathrm{1}}$ and the current comparator’s output $OUT$ is ‘0’. If the memory stores ‘1’，$I_{\mathrm{2}}=I_{\mathrm{1}}-I_{\mathrm{M}\mathrm{E}\mathrm{M}}$ where $I_{\mathrm{M}\mathrm{E}\mathrm{M}}$ is the current of the memory and $OUT$ is ‘1’. Because the drain current of $M_{\mathrm{5}}$ consistently equals $I_{\mathrm{1}}$，the voltage on the bus is clamped to avoid voltage crosstalk between adjacent bus lines.

Because there is only one different bit between two successive gray codes，the power consumption of column data W/R circuit decreases and the error rate is low compared with the binary-coded counterpart. Moreover，owing to adopting the 3T dynamic memories，the area occupied by the pixel-level ADC is small so that the charge handling capacity is large enough.

The proposed low-power DROIC is fabricated in 0.18 μm 1P5M CMOS process for an MWIR detector array. The DROIC microphotograph with a chip size of 11.5 mm$\times$13 mm is shown in Fig. 7（a）. The chip mainly comprises 640$\times$512pixel array with 15-bit pixel-level SS-ADC，ramp generator，column data W/R circuit，column memory array and data output MUX circuit. The pixel pitch is 15 μm and the pixel-level memories occupy about 54 $\mathrm{\mu }{\mathrm{m}}^{\mathrm{2}}$，meeting the pixel area limitation for charge handling capacity. The total integration capacitor $C_{\mathrm{I}\mathrm{N}\mathrm{T}}$ is about 740 fF and the charge-handling capacity is about 8.8 M$e^{-}$.

This DROIC is electrically tested by applying different DC inputs to simulate gray-scale images through the reset voltage signal $V_{\mathrm{R}\mathrm{S}\mathrm{T}}$ of $C_{\mathrm{I}\mathrm{N}\mathrm{T}}$. For low temperature testing，a test printed circuit board（PCB）shown in Fig. 7（b）is custom-designed，consisting of the part A with the DROIC chip，the part B with decoupling capacitors and the part C with excitation sources. $V_{\mathrm{R}\mathrm{S}\mathrm{T}}$ is generated by a high-precision DAC on part C and varies from 0.2 ~2.1 V. During the test，part A is placed in a liquid nitrogen container for cooling. Figure 8 shows the layout of 2×2 pixels.

The total power consumption is 48 mW under 1.8V/3.3V power supply at the frame rate of 120 Hz and the A/D conversion time is about 820 μs. The chip’s function is tested. $V_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}}$，which is output by a buffer，is captured by Agilent oscilloscope as shown in Fig. 9 and conforms to the expected design target. The digital output data are collected and processed by an FPGA. The data values are stable and are relative to $V_{\mathrm{R}\mathrm{S}\mathrm{T}}$. This demonstrates the data stored on the 3T dynamic memories are not lost at liquid nitrogen temperature.

Noise performance is an important concern for DROIC. The equivalent noise voltage $V_{n,\mathrm{R}\mathrm{O}\mathrm{I}\mathrm{C}}$ on $C_{\mathrm{M}\mathrm{O}\mathrm{S}}$ and $C_{\mathrm{S}}$ can be expressed by Eq. 6. $V_{n,\mathrm{C}\mathrm{M}\mathrm{P}}$ is the equivalent input noise voltage of the pixel comparator when $WRT<i,j>$ flips and $V_{n,\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}}$ is the output noise voltage of the off-pixel ramp generator. There are twice reset noise introduced after reset phase and integration phase. The power consumption and the area of the ramp generator are almost unlimited，so $V_{n,\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}}$ is designed to be far less than $V_{n,\mathrm{C}\mathrm{M}\mathrm{P}}$. The comparator is the main noise source. Though the proposed pixel-level power-self-adaptive pulse comparator consumes ultra-low average power，it consumes high enough power for low-noise and high-speed performance when $WRT<i,j>$ flips. Therefore，$V_{n,\mathrm{C}\mathrm{M}\mathrm{P}}$ is low.

Figure 10 presents a SNR histogram of the whole pixel array at the full well and the peak SNR（PSNR）is up to 84 dB. The equivalent noise voltage on the integration capacitor is about 116 μV. This demonstrates the proposed DROIC has good noise performance under low power consumption.

The gray-scale image with $V_{\mathrm{R}\mathrm{S}\mathrm{T}}=\mathrm{1.35}\mathrm{V}$ is shown in Fig. 11（a）and its fixed pattern noise（FPN）is shown in Fig. 11（b）. The measured FPN，which is defined as the ratio between the standard deviation and the mean，is about 0.28%. Through changing $V_{RST}$，the digital output versus the integration voltage curve is shown in Fig. 12. The non-linearity results are shown in Fig. 13 and the linearity is about 99.76%.

Table 1 shows the performance comparison between our proposed DROIC and some recent DROICs. The proposed DROIC is more competitive in power performance. Figure of merit（FoM）expressed in Eq. 7 adopts the definition as the power normalized to the number of pixels and the frame rate per step from Ref.［13］. This work，which achieves the lowest FoM among Ref.［5，11-12］，is leading in terms of energy efficiency.

A low-power 640$\times$512 DROIC with 15-bit pixel-level SS-ADC is proposed for cryogenic MWIR imagers and is fabricated in 0.18 μm CMOS process for verification. The pixel pitch is 15 μm. Cooperating with bottom-plate-sampling technique，a power-self-adaptive pulse comparator is presented for the pixel-level ADC to reduce power consumption. The power consumption of the comparator is nearly zero in most time and turns high enough only when the ramp signal approaches the integration voltage. In addition，its pulse output lowers the dynamic power consumed on the pixel memories because the A/D conversion results are stored only once. The 15-bit memories adopt a 3T dynamic structure and only occupy 54$\mathrm{\mu }{\mathrm{m}}^{\mathrm{2}}$，while the data retention capability is not a concern at liquid nitrogen temperature. The A/D conversion results stored in the pixel memories are read out to column in current-mode to avoid voltage crosstalk between adjacent bus lines. The experimental results demonstrate that the DROIC consumes 48mW at 120 fps. The pixel SS-ADC is area-efficient and the proposed DROIC achieves high charge handling capacity of 8.8 Me^-. The peak signal-to-noise ratio is 84dB at the full well. These results prove that the proposed DROIC is effective in lowering power consumption while keeping high SNR.