In order to implement high speed error correction coding in 400 Gb/s Ethernet physical coding sublayer（PCS）, a recursive Reed-Solomon（RS） coding circuit is designed. By combining recurrence factor, input data and register data, the result of recursive RS coding circuit can be obtained. VCS+Verdi software is used to simulate the traditional RS coding circuit and the recursive RS coding circuit, and the Nangate 45 nm open source process is used for comprehensive testing. The simulation and test results show that compared with the parallel RS（544，514） coding circuit, the recursive RS coding circuit can greatly reduce the time cost. The area of the 32-channel recurrent RS（544，514） coding circuit is reduced by 68% and the power consumption is reduced by 60%.