A synapse circuit with low power consumption, high energy efficiency and compact structure was designed in a 65 nm CMOS technology. It could be used in Spike Neuron Network (SNN) system. A switched capacitor circuit structure was used in the synapse circuit to receive directly the pulse signal from the neuron circuit. The weight of synapse could be adjusted by Spike Timing Dependent Plasticity (STDP) learning rule, and the tunable asymmetric of the weight learning window was realized, so that the synaptic circuit could adapt to different applications. The simulation results showed that the synaptic circuit consumed around 0.4 pJ/spike.