A high power wideband SPDT RF switch was designed and implemented in a 013 μm CMOS SOI process. The RF switch was an absorption RF switch with a series and parallel topology. The negative voltage bias design was applied to reduce the insertion loss and improve isolation. The stacked-MOSFET structure was applied to improve the input 1 dB compression point of the switch. The test results show that in the frequency range from 100 MHz to 12 GHz, the insertion loss is less than 15 dB, the minimum isolation is 31 dB, and the minimum input 1 dB compression point is 40 dBm. The chip size is 11 mm × 11 mm.