This paper presents a theoretical study on the influences of the device structure parameters on the damage progress of the silicon NPN monolithic composite transistor induced by injection power. The silicon NPN monolithic composite transistors (composed by two successive transistors, T1 and T2) with three different structural parameters are established utilizing the circuit simulator, Sentaurus-TCAD. The dependences of the damage energy threshold and the damage power threshold required to cause the device failure on the pulse-width are obtained. The results show that higher power threshold and more energy are needed to damage the device if the area of the T2 transistor is larger. A study of the damage mechanism is conducted based on the variation analysis of the distributions of the electric field, current density, and temperature in the device. It is found that the distributions of the electric field, current density, and temperature become more dispersed as the area of the T2 transistor increases. It is concluded that when the overall area of the silicon NPN monolithic composite transistor is constant, and as the area ratio of the T2 transistor and the T1 transistor increases, the device becomes less vulnerable to damage. Moreover, the emitter resistor Re has a significant effect on the burnout time. The simulated burnt spot position of the transistor is in good agreement with the experimental result.