Based on the EPC class-1 generation-2 protocol, the system specifications of the frequency synthesizer working in the global UHF RFID band was analyzed. By using the standard 0.18 μm CMOS process and integrating a new adaptive frequency calibration module, a low phase noise, fast locking fractional frequency synthesizer was designed. The LC-VCO was based on the tailless current source topology and utilized the second harmonic filtering technology to significantly reduce the phase noise in band. In addition, the adaptive frequency calibration circuit was different from the traditional binary comparison method. It was based on a novel successive comparison method to reduce the comparison time of the 4-bit digital logical control voltage of the VCO. Therefore, the control words of the VCO could be quickly determined and the locking time could be improved. The simulation results show that the locking time is only 6.3 μs during the adaptive calibration period, the overall locking time of the loop is lower than 23.2 μs, its phase noise performance is -106.3 dBc/Hz at 100 kHz frequency offset and -126.1 dBc/Hz at 1 MHz frequency offset, and the overall power consumption is 84 mW. Compared with the performance of the recently released advanced CMOS fractional-N frequency synthesizer, the proposed one achieves considerable phase noise performance, and works with shorter locking time and lower power consumption.