Recent technological advances, the photoelectric detectors based on GaN with unique optical, electrical and structural properties have gradually matured. Because of their wide tunable direct bandgap, good carrier transport properties, high breakdown fields chemical stability and high robustness, AlGaN based solar-blind UV detector have been studied extensively in ultraviolet (UV) photodetectors. And UV imaging systems have been widely used in defense, scientific research, missile warning, offshore oil monitoring, spectroscopy, chemical and biological threat detection, environmental monitoring, astronomy and so on^[1-4].

Readout Integrated Circuit (ROIC) is one of the most important parts of UVFPA. And due to the amount of pixels increasing rapidly for large formats resulting in the power consumption of readout circuit increases speedy, the realization of low power consumption has become one of the key challenges for ROIC design. To realize low power, the dynamic windowing and transposition methods have been proposed with the columns outside the window and the unused buffers are powered down^[5]. Through proper design of readout timing and using two operating modes in column amplifiers to reduce power consumption have also been proposed^[6]. What’s more, direct injection (DI), source-follower per detector (SFD) structures in pixels widely used to decrease power consumption^[7-9]. To reduce power consumption for larger and larger pixel arrays, the design of low power cell circuit is necessary. In this study, a readout circuit is represented for 1 024×1 024 UVFPA of low power consumption which fabricated in SMIC 0.18 µm 1P6M mixed signal process. The CTIA structure in pixels is adopted by a current adjustment single-terminal amplifier to realize low power consumption. This circuit supports several adjustments optimize power for better performances. The chip achieves a minimum power only 67.3 mW at 2 MHz all frame rate in a 1 024×1 024 FPA with 18 µm-pitch.

The system architecture of the ROIC with snapshot integration mode is shown in Fig.l, including pixel array, column level shift, column buffer, output buffer, current bias, row and column select logic circuit, etc. The readout circuit mainly divides into analog modules, digital modules and whole chip ESD protection modules^[10]. Analog modules consist of 1 024 × 1 024 pixel arrays, column stage, output driver buffer and bias modules. Digital modules consist of row select, column select and control logic modules. Analog and digital modules are supplied by different power buses part surrounding the chip respectively to prevent the cross-talk and noise between analog and digital signals.

Meanwhile, the whole chip ESD protection network mentioned in this paper are separated into logic and analog ESD protection modules. They are placed at the left and bottom part of the chip separately. The analog and Logic ESD modules are supplied by analog and digital supply lines, respectively, to decrease crosstalk effect. And various methods are adopted to improve robustness of the chip such as multi power clamps, dummy devices and top metal as light barrier covered the whole chip, etc.

This designed readout circuit has adjustable integration time, gain of CTIA and internal bias supplies, and has multi outputs. In addition, this circuit features snapshot mode with integrate-while-read (IWR) and integrate-then-read (ITR) operation that all pixels integrate simultaneously per integration period.

Though direct injection (DI), source-follower per detector (SFD) structures in pixels widely used to decrease power consumption, but they can’t provide constant bias voltage for photodiode resulting in lower conversion factor. Therefore, the CTIA is adopted with stable bias voltage, good linearity, high injection efficiency and wide detecting range. What’s more, to realize larger format FPA of low power, the design of ultra-low-power pixel is the key point, so a single-terminal amplifier using the cascode configuration instead of two- terminal amplifier as pixel amplifier in this paper to optimize the power consumption as small as possible. What’s more, it substantially reduces the power consumption by operating amplifier transistors under subthreshold region and the smallest operational current of CTIA in pixel unit is only 8.5 nA. The current can be expressed as:

The parameter η is subthreshold swing coefficient, and is calculated to between 1 and 3. The process parameters of oxide capacitance per unit area C_ox, surface depletion-layer capacitance C_si and interface-trapped capacitance C_SS. The parameter k is Boltzmann's constant, T is the absolute temperature in degrees Kelvin, and q is the absolute value of electron charge. In addition, transistor has a linear relationship between the transconductance and the drain current in subthreshold region. Thus, the transconductance to drain current ratio is maximized according to Eq. (5).

Figure 2 shows the pixel arrays and column level circuits architecture with a level shift circuit. The photo current is integrated onto the integration capacitor which can be selected as 10 fF and 110 fF by S1 switch for different conversion gains in each pixel at the same time in snapshot mode. The CTIA transfers the charge in pixel to voltage signal, which will be sampled and held by the pixel S/H circuit consists of S2 and C3, and then be read out by the SF pixel buffer row by row with row pitch at 18 µm ×18 µm including a 6 µm × 6 µm mini pad, and the minimum static current is even 8.5 nA per pixel in the proposed design due to single-terminal amplifier has one current branch. Thus, it benefits for realizing low power.

The column stage circuits include level shift, column S/H and column buffer circuit. The SF buffer in pixel unit shares a common current source load with other 1 023 pixel cells in the same column, and the pixel signal is transferred through SF buffer. Afterwards, the same current source is also used for level shift circuit, which compensates the voltage drop caused by SF buffer, to save lots of consumption, and thus becomes the second way to reduce power consumption. Compared to pixel S/H circuit which isolates outputs among pixels and get more flexible readout mode, the column S/H and column buffer circuits separate the column output from all pixel outputs to achieve low noise performance.

The third method to decrease power dissipation is the novel design of column buffer, which is shown in Fig.3. In the proposed design, the power control switch S6 is adopted, where is in the branch of current mirror to control the tail current I₀. The tail current source of column amplifier is divided into two parts, one is I0 and the other is I₁, which I₀ is much bigger than I₁. When the column selection switch is latched on and delivered pixel signal normally, the switch S6 is latched on simultaneously, both branches provided current with the sum of I₀ and I₁ to amplifier. When the column selection switch is latched off and the switch S6 is latched off at the same time, the branch circuit of large tail current I₀ is closed, and only the small current I₁ is left to supply for amplifier. The value of I₁ is only 190 nA calculated by Eq.(1), and to make sure the NMOS transistor of M1 working in the saturation region, the bias voltage V_b2 is a little bit higher than V_TH and the channel length is larger than the width of M1. In this way, the proposed column amplifier can greatly reduce the power consumption of the whole chip.

Generally, these methods were introduced in UVFPA readout circuit to realize low power consumption for large format arrays. Meanwhile the ROIC also supports bias current adjustments to optimize power dissipation for better performances. The ROIC has a 3-bit digital-to-analog converter (DAC) on chip which generates adjustable bias-current for allover chip. Fig.4 shows the architecture of whole chip bias supply, DAC on chip decided the master bias supply by control bits B₀₁-B₀₃. Three switches B₁₁-B₁₃ which is used to control power dissipation with the master bias current for the CTIA amplifier bias in the unit pixel. While another switches B₂₁-B₂₂ to adjust bias currents for the analog signal path including level-shift, column buffer and output buffer circuits.

The total power consumption can be calculated in Eq. (2).

Where P_pixel is the power of per pixel; P_column is the power of output-stage; P_bias is the power of current bias circuit; P_logic is the power of digital control circuit which can be ignored; P_column refers to power of one column-stage circuit which contains SF power P_sf; level-shift power P_ls and column buffer P_cb. M is column and N is row that both of them are equal to 1 024 in this ROIC. There are totally 8 output buffers in this design and every 128 column shares an output buffer, so n equals 8 in this equation. As mentioned in this equation we can see that the most part of power dissipation comes from pixel arrays and the lower power of the pixel, the lower power of the whole chip.

The novel design of common current source load for SF buffer in pixels and level shift circuits is used to decrease power consumption for this ROIC, the total power consumption can be changed to calculated in Eq. (8). Compared to Eq.(7), the power of P_sf reduced significantly.

Table 1 gives a comparision of power consumption in the previous paper^[11] and this paper.

Compared to that, the pixel current reduces from 499 nA to 8.5 nA after optimizing design, which improved the power consumption for large pixel arrays application. What is more, the total consumption is also reduced greatly in Tab.1.

The UVFPA readout circuit is designed and fabricated in SMIC 0.18 µm 1P6M mixed signal process with 3.3 V supply. Figure 5 shows the die photograph of 1 024×1 024 pixels format UV FPA ROIC chip, which the die size is 19.30 mm×20.17 mm. The 1 024×1 024 pixel detector arrays with 18 µm×18 µm pixel pitch would connect this ROIC chip that take the 2×2 pixels mirror symmetry layout as a unit layout, together through Indium with 6 µm× 6 µm mini pad.

Figure 6 shows the test platform, which consists of DC power supply, serial data timing generator, digital oscilloscope, acquisition card and PCB board of test. As mentioned in section2, the minimum current of the whole chip is 20.4 mA at 2 MHz readout rate with 3.3 V power supply, so the total power consumption is only 67.3 mW due to apply those modified design in ROIC.

The measurement results of 1 024×1 024 ROIC with eight outputs by acquisition card NI6366 are shown in Fig.7. Meanwhile the raw data come from acquisition card are made in an intensity graph of all frame are also illustrated.

The performances include operate mode, output swing range, integration capacitor charge capacity and power supply, etc. The summarized specifications of the 1 024×1 024 readout circuit are detailed in Tab.2. It can be seen that the ROIC makes two gain selections with 10 fF and 110 fF integration capacitors which charge capacities are 0.11Me- and 1.23Me- respectively per pixel with 1.8 V output range.

In this paper, these methods are adopted to optimize power consumption for UVFPA readout circuit, which are single-terminal amplifier with static current 8.5 nA as CTIA amplifier, common current source load for SF buffer in column pixels and level shift circuits, and time-sharing tail current source for column buffer. As well as, the UVFPA ROIC has a format of 1 024×1 024 and pixel pitch of 18 µm with 10 fF and 110 fF selectable integration capacitors with a variable integration time. Meanwhile, the ROIC operates in snapshot integration mode which has Integrate-Then-Read (ITR) and Integrate-While-Read (IWR) read modes respectively. Above all, the ROIC accomplished an ultra-lower power consumption of 67.3 mW at 2 MHz all frame rate in a 1 024×1 024 FPA with 3.3 V supply voltage. What’s more, it has been fabricated in SMIC 0.18 µm 1P6M mixed signal process and achieved better performances.