• Photonics Research
  • Vol. 12, Issue 3, A11 (2024)
Shuqing Lin1, Yanfeng Zhang1,2,*, Zhaoyang Wu1, Shihao Zeng1..., Qing Gao1, Jiaqi Li1, Xiaoqun Yu1 and Siyuan Yu1|Show fewer author(s)
Author Affiliations
  • 1State Key Laboratory of Optoelectronic Materials and Technologies, School of Electronics and Information Technology, Sun Yat-sen University, Guangzhou 510275, China
  • 2Hefei National Laboratory, Hefei 230088, China
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    DOI: 10.1364/PRJ.507548 Cite this Article Set citation alerts
    Shuqing Lin, Yanfeng Zhang, Zhaoyang Wu, Shihao Zeng, Qing Gao, Jiaqi Li, Xiaoqun Yu, Siyuan Yu, "Power-efficient programmable integrated multiport photonic interferometer in CMOS-compatible silicon nitride," Photonics Res. 12, A11 (2024) Copy Citation Text show less
    Fabrication and characterization of the suspended phase shifter. (a) Post process for phase shifter’s suspension. (b) The SEM image of a cross-sectional view of a fabricated suspended phase shifter. (c) Normalized optical transmission against the heating power when employing a suspended or a normal phase shifter within the MZI. (d) The numerical and experimental curves of tuning efficiency of suspended and normal phase shifters. (e) The temporal optical response curve of a suspended or a normal phase shifter to square-wave voltage signals. (f) Phase errors induced by thermal crosstalk in both normal and suspended phase shifters.
    Fig. 1. Fabrication and characterization of the suspended phase shifter. (a) Post process for phase shifter’s suspension. (b) The SEM image of a cross-sectional view of a fabricated suspended phase shifter. (c) Normalized optical transmission against the heating power when employing a suspended or a normal phase shifter within the MZI. (d) The numerical and experimental curves of tuning efficiency of suspended and normal phase shifters. (e) The temporal optical response curve of a suspended or a normal phase shifter to square-wave voltage signals. (f) Phase errors induced by thermal crosstalk in both normal and suspended phase shifters.
    (a) Schematic diagram of the a 6-mode linear photonic processor using Clements’ architecture. (b) Microscope image of the 6-mode interferometer with suspended phase shifters.
    Fig. 2. (a) Schematic diagram of the a 6-mode linear photonic processor using Clements’ architecture. (b) Microscope image of the 6-mode interferometer with suspended phase shifters.
    Calibration and characterization of the device. (a) The experimental testing setup (TLS, tunable laser; FPC, fiber polarization controller; DUT, device under test; PM, power meter; FPGA, field programmable gate array; DAC, digital-to-analog converter). (b) Detailed view of the device under test on a coupling stage. (c) Transmittance spectrum of the calibrated device. (d) Statistics of the half-wave consumption of the internal phase shifters. (e) Statistics of the extinction ratio of all the MZIs. (f) Prediction of insertion loss and power consumption with increasing scale for our device.
    Fig. 3. Calibration and characterization of the device. (a) The experimental testing setup (TLS, tunable laser; FPC, fiber polarization controller; DUT, device under test; PM, power meter; FPGA, field programmable gate array; DAC, digital-to-analog converter). (b) Detailed view of the device under test on a coupling stage. (c) Transmittance spectrum of the calibrated device. (d) Statistics of the half-wave consumption of the internal phase shifters. (e) Statistics of the extinction ratio of all the MZIs. (f) Prediction of insertion loss and power consumption with increasing scale for our device.
    Experimental 6-mode linear transformation. (a) Measured matrices for all integer powers of 6D cyclic transformations (X-gates). (b) Theoretical and measured transmission matrices of arbitrary 6D unitary transformations SU(6)1 and SU(6)2.
    Fig. 4. Experimental 6-mode linear transformation. (a) Measured matrices for all integer powers of 6D cyclic transformations (X-gates). (b) Theoretical and measured transmission matrices of arbitrary 6D unitary transformations SU(6)1 and SU(6)2.
    (a) Schematic of the lateral layout of phase shifters. (b) Phase shifters with a dense lateral arrangement. (c) Phase shifters with a reasonable lateral spacing.
    Fig. 5. (a) Schematic of the lateral layout of phase shifters. (b) Phase shifters with a dense lateral arrangement. (c) Phase shifters with a reasonable lateral spacing.
    Schematic diagram of matrix decomposition for a rectangular interferometer. (a) Correspondence of the 2D unit matrices with the basic unit blocks and the order of their multiplication. (b) Connection of external phase shifters in slices.
    Fig. 6. Schematic diagram of matrix decomposition for a rectangular interferometer. (a) Correspondence of the 2D unit matrices with the basic unit blocks and the order of their multiplication. (b) Connection of external phase shifters in slices.
    Calibration flow of the external phase shifters for our SISO testing strategy.
    Fig. 7. Calibration flow of the external phase shifters for our SISO testing strategy.
    Configuration for the integer powers of cyclic transformation (X-gate).
    Fig. 8. Configuration for the integer powers of cyclic transformation (X-gate).
    DevicePlatformManufacturerScaleTuning EfficiencyTuning SpeedInsertion LossReference
    Universal linear processorSOIIMEC4×415  mW/π<4  kHz6.9 dB[23]
    DTU4×46  mW/πkHz11.5 dB[24]
    ANT4×455  mW/π\17.5 dB[16]
    AMF8×835 or 3.05amW/π<10  kHz13.36 dB[15]
    Triplex (SiNx+SiO2)Lionix4×4296  mW/π\10.5 dB[16]
    8×8\\8 dB[20]
    12×12385  mW/π<kHz3.4 dB[21]
    20×20\\2.9 dB[22]
    SiNx (LPCVD)Ligentec4×4<100  mW/π [25]\8 dB[26]
    SiNx (ICP-CVD)SYSU6×612  mW/π<kHz6 dBThis work
    SwitchSiNx (PECVD)\4×4130  mW/π<20  kHz7.2 dB (TE mode), 5.7 dB (TM mode)[27]
    \5×5>300  mW/π<kHz8 dB[28]
    Table 1. Overview of MZI-Based Photonic Processors Working around 1550 nm
    Shuqing Lin, Yanfeng Zhang, Zhaoyang Wu, Shihao Zeng, Qing Gao, Jiaqi Li, Xiaoqun Yu, Siyuan Yu, "Power-efficient programmable integrated multiport photonic interferometer in CMOS-compatible silicon nitride," Photonics Res. 12, A11 (2024)
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