The causes of VLSI design rule check violation (DRC) in advanced technology are very complex, which makes the congestion map of global routing can’t reflect the distribution of DRCs accurately. In this paper, a deep-learning based approach is proposed for predicting DRCs. Pin, net and macro information of placement rather than global routing were used as features. Then, these features were trained by a convolutional network after being processed by CSMOTE. Finally, M2 short and cut group space were predicted by this model. The method was tested in a real industrial design in advanced technology node. Experimental results show that the accuracy and F1 score on M2 short is 93.4% and 0.78 respectively, while 92.5% and 0.78 on cut group space.