A multiple-columns-shared-parallel pipelined successive approximation register (SAR) analog-to-digital converters (ADC) was presented for high speed CMOS image sensors (CIS) application. As the pixels in 8 columns shared one pipeline-SAR ADC, the layout was no longer restricted to double pixel pitches, and can be implemented within 16 pixel pitches. Asynchronous logic was implemented to improve the conversion speed of multiple-columns-shared-parallel pipeline-SAR ADC. A half-gain multiplying digital-to-analog converter (MDAC) was used for the residue amplification to relax the requirements for the operational amplifier (opamp), and correlated level shift technique was also used for more precise amplification. The 12-bit resolution was divided by 6-bit coarse and 7-bit fine SAR sub-ADC with 1-bit stage redundancy calibration between coarse and fine steps. Input full scale voltage was 1 V. The ADC was designed in 0.18 μm 1P4M CIS process, and occupied 0.204 mm2 for 8 columns. The simulated results of the ADC showed a SNDR of 72.6 dB with a 229.7 kHz input and 71.7 dB with a 4.16 MHz input at 8.33 Msps. It dissipated 4.95 mW at 1.8 V supply and the FoM was 172.5 fJ/conversion-step. Because the pixel pitch is only 7.5 μm and the process has only 4 metals, this proposed 12-bit multiple-columns-shared-parallel pipeline-SAR ADC is quite suitable for the high speed CIS.