In recent decades，the demand for millimeter-wave and submillimeter-wave power sources has surged，driven by the expanding application of terahertz technology in fields such as remote sensing，high-speed communication，and radio astronomy^［1-4］. Currently，there are two primary methods for generating terahertz sources：optical solutions，including far-infrared lasers，femtosecond infrared lasers，photoconductors，and Quantum Cascade Lasers（QCLs）^［5-7］，and electronic solutions，comprising vacuum electronic devices^［8-11］and solid-state circuits^{［12，13］}. Due to the high quality，low cost，high reliability，and compact structure of frequency multiplier chains made from Schottky diodes，they have emerged as the leading choice for terahertz source solutions.

As the mainstream technological solution for terahertz sources，research on Schottky diode frequency doublers has been increasing. The principle of frequency doubling with Schottky diodes primarily utilizes the diode's nonlinear characteristics，including varactor and varistor properties，to generate harmonic components at corresponding frequencies，which are then extracted and output through an E-plane waveguide probe structure. Varactor diodes excel in delivering higher power outputs with superior efficiency，whereas varistor diodes are distinguished by their ability to provide wider bandwidths. Balanced frequency doublers^［14-18］ and balanced triplers ^［19-23］ have become standard topological structures for frequency multiplication，as their inherent topologies suppress unneeded harmonics and reduce the need for filtering structures，thereby enhancing broadband characteristics and greatly improving frequency multiplication efficiency. To date，all-solid-state frequency multiplier chains utilizing Schottky diodes have reached operational frequencies of up to 2.7 THz ^［24］. To ensure sufficient driving power for the final stage of the frequency multiplier chain，it is crucial that the driving power input by the preceding stages is adequately high. However，limitations due to the number of anode junctions and the power capacity of the materials impose an upper limit on the power capacity of individual circuits. Techniques such as in-phase power combining^［25-29］and on-chip power combining^［30］ have been proposed to solve this problem. However，this results in a considerable expansion of the circuit's scale，subsequently leading to a marked increase in the duration required for nonlinear simulations throughout the design process. Consequently，optimizing simulation design methods is crucial for enhancing the design efficiency.

The popular approach in terahertz circuit design combines three-dimensional electromagnetic field models with diode SPICE models through the coaxial probe method，enabling accurate prediction of the circuit performance. However，the specific implementation processes of different methods each have their own variations. The subdivision design method（SDM）^{［31，32］}divides the circuit into multiple independent unit structures，each optimized through 3D-EM simulations. The global design method（GDM）^［33］ deconstructs the entire circuit into a series of variables that can be optimized，increasing the degree of freedom for optimization but also the computational load，requiring substantial system resources. The half-global design method（HGDM）^［34］ merges these strategies，balancing computational load with optimization flexibility.

However，regardless of how 3D-EM is segmented into units in these mentioned design methods，the final simulation optimization still occurs within harmonic balance simulation software，thus the simulation speed is constrained by the speed of harmonic balance simulations. Recently，some efforts have been made to separate linear and nonlinear circuits ^{［35，36］} to increase simulation speed. However，these methods only separate the waveguide and circuit components，resulting in the inability to optimize the matching structures near the diode units within the linear circuit. This limitation，crucial for frequency doubling circuit performance，consequently increases the workload.

This paper introduces an impedance matching method that distinctly separates linear circuits from nonlinear circuits. The principal concept isolates the nonlinear circuit from the impedance matching process，connecting the two through the diode's harmonic embedding impedance in the linear circuit as determined by nonlinear simulations. This approach significantly improves simulation speed. To validate the accuracy and practicality of this design concept，a 340 GHz balanced frequency doubler circuit was designed and fabricated.

The balanced frequency doubler consists of a pair of in-phase，parallel-connected diodes mounted on the E-plane of the input waveguide，with the output signal transmitted to the output waveguide by means of an E-plane probe. Its unique topological structure allows the currents generated by odd harmonics to circulate between the diodes and the ground provided by the cavity，effectively making the entire diode unit act like a dipole antenna that excites TE modes in the waveguide. Meanwhile，the currents from even harmonics can generate TEM modes along the direction of the transmission line. This configuration results in mode isolation between the input fundamental signal and the output second harmonic signal，as well as impedance isolation. Consequently，input and output matching can be designed independently without concern for their coupling effects.

According to the principles，the design of a balanced frequency doubler circuit can be segmented into three parts：initially，individual harmonic balance simulations of the diodes are performed to determine their best operating harmonic embedding impedance；subsequently，the previously determined harmonic embedding impedance is utilized to design the input and output matching circuits separately；finally，the input and output matches are integrated into a complete circuit，and a comprehensive harmonic balance simulation is performed to predict the circuit's performance. The design process is illustrated in Fig. 1.

For frequency doublers based on Schottky diodes，the diode's parasitic and intrinsic parameters significantly impact the performance of the frequency doubler. To ensure the doubler operates optimally at 340 GHz，with the maximum output under a standardized 100 mW input，we optimized the intrinsic parameters of the diode based on measured data from a series of Schottky diodes with different diameters. The final intrinsic parameters of the diode are presented in Table 1.

Subsequently，harmonic balance simulations are performed on the diode model to extract both the fundamental and second harmonic embedding impedances，as depicted in the HB simulation section of Fig. 1. Sampling of the optimal harmonic embedding impedances within the 155-185 GHz frequency range was carried out through harmonic balance simulations，targeting the desired output efficiency at these frequencies. This process ultimately yielded a series of embedding impedances，which represent the diode's optimal embedding impedances within this frequency band. Given the continuity of embedding impedances and their gradual variation with frequency，as illustrated on the Smith chart，larger steps can be taken between frequency points to reduce simulation time without compromising the accuracy of the results. The final normalized embedding impedances are shown in Fig. 2.

As mentioned in Section 2.1，the input fundamental signal operates in the TE₁₀ mode，while the output second harmonic signal travels in the TEM mode. Their mode orthogonality ignores the need for an additional filter，reducing the complexity of the matching process. Moreover，the isolation between input and output impedances minimizes their mutual influence，allowing for the independent optimization of the input matching network.

As shown in Fig. 3，the initial step involves determining the parameters of the waveguide cavity where the diode cell is suspended. The width of the waveguide，a，is primarily determined by the input frequency，while the height of the waveguide，b，is influenced by the ease of impedance matching as well as the cutoff concerns of the TM₁₁ mode at the output frequency. Other parameters that significantly affect the input impedance，such as the distance from the diode plane to the short-circuit plane of the input waveguide and the dimensions for the input matching waveguide，can be optimized in an S-parameter simulation after parameterization，as illustrated in the schematic in Fig. 4. Connecting the AC source to the diode’s port optimizes their average impedance. It is crucial to note that the source impedance here is conjugate to the impedance extracted from the previous harmonic balance simulations. Incorrect setting of this impedance may lead to discrepancies from expected results.

Furthermore，the transmission structures in the output matching circuit might affect the field distribution of the TE₁₀ mode，thereby influencing the transmission constants and characteristic impedance of the TE₁₀ mode，as shown in Fig. 5（b）. To prevent the transmission line structure of the output circuit from affecting the input impedance，two methods can be used：the first is to determine the maximum line width that does not affect the TE₁₀ mode through simulation；the second is to incorporate this transmission line into the input matching circuit after obtaining the output matching circuit，and then iterate to eliminate this effect.

Ultimately，the dimensions of the various parts of the input matching circuit obtained through simulations are shown in Fig. 5（a）. It is worth noting that the transmission line in Fig. 5（a）is primarily used for output circuit matching. However，considering the effect on the input mode TE₁₀，as shown in Fig. 5（b），this effect needs to be reflected in the input circuit to iterate the dimensions of the input matching waveguide，thereby eliminating the influence. Consequently，the dimensions are determined by the output matching circuit. Additionally，Fig. 5（c）illustrates the relationship between the impedance provided by the input matching network and the optimal input impedance of the diode. The blue line represents the impedance provided by the input matching network，while the red circle represents the optimal embedded impedance of the diode extracted through harmonic balance simulation.

The output matching circuit can be divided and designed in two parts：one from the diode to the suspended microstrip line in the channel，and the other encompassing the output probe transition，which includes a DC filter. These two parts are connected by introducing a fixed load impedance，Z_L，in the middle to simplify the complexity of output matching. The load impedance is determined by the suspended microstrip line in the channel. Thus，when combining the two circuit parts，merely adjusting the length of the suspended microstrip line can minimize reflections between the two subcircuits. The specific principle is illustrated in Fig. 6. The principle of the matching circuit for the first section，from the diode to the suspended microstrip line in the channel，is shown in Fig. 6. The second part of the matching circuit，including the output probe transition，DC filter，and the output waveguide matching section，is illustrated in Fig. 7（a）. The connecting part between them is represented by Z_L.

Diverging from traditional high-low impedance filters，this design employs a CMRC（Compact Microstrip Resonant Cell）filter for the DC filtering section，aiming to minimize the overall length of the chip while ensuring robust RF suppression capabilities to ease assembly challenges. The resulting integrated output circuit's waveguide matching section is displayed in Fig. 7（a），with details of the monolithic integrated circuit shown in Fig. 7（b）. Additionally，the relationship between the impedance achieved by the output matching network and the diode's output impedance is illustrated in Fig. 7（c）.

After separately designing the input and output matching circuits，combining these two sections forms the complete frequency doubler circuit，which includes the monolithic circuit and the metal cavity. An E-plane split-waveguide block is produced through computer numerical control（CNC）milling technology and is further processed by electroplating. The diode chip is mounted on the split block and aligned through beam leads to ensure its correct placement. This step is critical，as the accuracy of alignment directly influences performance. Subsequently，the DC beam leads are connected to the chip capacitors and through capacitors to establish the DC pathway for the frequency doubler. Lacking thermo-compression bonding facilities，conductive adhesive is used to attach the beam leads to the cavity. However，this approach does not offer sufficient strength，making the chip prone to shifting during the disassembly of the cavity. This may also explain the significant discrepancies between our empirical results and the simulations. The fully assembled frequency doubler is illustrated in Fig. 8.

The constructed test system is shown in Fig. 9. The driver source chains includes a synthesizer，followed by an 81-86 GHz sextupler module，which is then connected to a 170 GHz doubler. The output signal is amplified by a GaN-based HEMT amplifier with a gain of about 10dbm，allowing the chains to provide an output power of approximately 72-150 mW in the 162-175 GHz band. Both the source power calibration and the output power measurement are performed by an Erickson PM4 power meter. To achieve optimal performance of the doubler，we measured the output power and frequency characteristics of the frequency multiplier at a series of different bias points，and the final output curve represents the maximum output power recorded at each frequency point.

Figure 10（a）displays the actual input power versus the measured output power of the 340 GHz frequency doubler. Within the range of 330-342 GHz，the output power exceeds 13 mW，reaching a maximum output power of 21.8 mW at 334 GHz. Figure 10（b）shows a comparison between the measured efficiency and the simulated efficiency using different series resistances. It is known from Refs.［19，37］that series resistance is crucial to circuit performance，and the resistance obtained from DC measurement is often underestimated for RF simulations. According to the comparison，we found that the simulation results using the adjusted series resistance align better with the test results. Moreover，the test results indicate a sharp decrease in output power above 344 GHz，while a slight increase in output efficiency is observed below 330 GHz.

As shown in Fig. 8，the supporting beam lead is not aligned with the output waveguide but is instead shifted into the input waveguide，which may be the main cause of the sharp drop in output. Based on this issue，we conducted a simulation analysis of the impact of lateral assembly errors of the doubler chip on the performance of the frequency doubler，as shown in Fig. 11. It can be observed that when the lateral shift is around 10 µm，the output results do not change significantly. However，when the shift exceeds 10 µm，both the output efficiency and bandwidth of the doubler start to decline，especially in the case of forward shifting，where the beam lead moves toward the output waveguide. In this case，the decline in output efficiency and bandwidth becomes very noticeable，which aligns well with the situation shown in Fig. 8. Therefore，during the manufacturing process of the frequency doubler，it is crucial to control the assembly error tolerance within 10 µm as much as possible. Additionally，as shown in Fig. 12，there is a notch in the output waveguide of the machined lower half of the cavity，which could unpredictably affect the output.

Table 2 presents a comparison between the frequency doubler proposed in this paper and those designed using other methods. Unlike approaches that optimize linear and nonlinear circuits together，the method of separating linear and nonlinear circuits adopted in this work ensures both efficiency and flexibility while achieving commendable performance.

In this paper，a strategy to boost the design efficiency of terahertz frequency multipliers is proposed. This method separates the circuit into linear and nonlinear parts for distinct simulations. By using the diode's nonlinear properties in the linear circuit's embedding impedance，it connects the two parts. This separation of harmonic balance from S-parameter simulations helps to reduce simulation time. Following this strategic framework，a 340 GHz frequency doubler was developed and subjected to empirical validation. Performance evaluations revealed that within a bandwidth of 330 GHz to 342 GHz，the efficiency of the device consistently surpasses 10%，with the input power oscillating between 98 mW and 141 mW，and the output power starting from 13 mW. Remarkably，with an input power set at 141 mW，the device achieved a peak output of 21.8 mW at 334 GHz，translating to an efficiency rate of 15.8%. The practical application of this frequency doubler effectively demonstrates the viability of the suggested approach. This technique promises adaptability for a wide range of applications in terahertz circuits，particularly for complex harmonic structures like mixers and compact modules.