[1] SATPATHY S K, MATHEW S K, KUMAR R, et al. An all-digital unified physically unclonable function and true random number generator featuring self-calibrating hierarchical von neumann extraction in 14-nm tri-gate CMOS [J]. IEEE J Sol Sta Circ, 2019, 54(4): 1074-1085.
[3] MARTIN H, PEDEO P L, TAPIADOR J E, et al. A new TRNG based on coherent sampling with self-timed rings [J]. IEEE Trans Indust Inform, 2016, 12(1): 91-100.
[4] WIECZOREK P Z. Lightweight TRNG based on multiphase timing of bistables [J]. IEEE Trans Circ Syst I: Regul Papers, 2016, 63(7): 1043-1054.
[5] SURESH V B, BURLESON W P. Entropy and energy bounds for metastability based TRNG with lightweight post-processing [J]. IEEE Trans Circ Syst I: Regul Papers, 2015, 62(7): 1785-1793.
[6] WIECZOREK P Z, GOLOFIT K. True random number generator based on flip-flop resolve time instability boosted by random chaotic source [J]. IEEE Trans Circ Syst I: Regul Papers, 2018, 65(4): 1279-1292.
[8] ISO/IEC 20897:2020, Information technology - Security techniques - Security requirements test and evaluation methods for physically unclonable functions for generating nonstored security parameters [S]. 2020-12.
[9] GAO Y, MA H, ABBOTT D, et al. PUF sensor: exploiting PUF unreliability for secure wireless sensing [J]. IEEE Trans Circ Syst I: Regul Papers, 2017, 64(9): 2532-2543.
[10] RAHMAN T, RAHMAN F, FORTE D, et al. An aging-resistant RO-PUF for reliable key generation [J]. IEEE Trans Emerg Topics Comput, 2016, 4(3): 335-348.
[11] SAHOO S R, KUMAR S, MAHAPATRA K, et al. A novel aging tolerant RO-PUF for low power application [C] // IEEE iNIS. Gwalior, India. 2016: 187-192.
[12] SHIFMAN Y, MILLER A, KEREN O, et al. An SRAM-based PUF with a capacitive digital preselection for a 1E-9 key error probability [J]. IEEE Trans Circ Syst I: Regul Papers, 2020, 67(12): 4855-4868.
[13] VAIDYANATHASWAMI R, THANGARAJ A. Robustness of physical layer security primitives against attacks on pseudorandom generators [J]. IEEE Trans Commun, 2014, 62(3): 1070-1079.
[14] LARIMIAN S, MAHMOODI M R, STRUKOV D B. Lightweight integrated design of PUF and TRNG security primitives based on eflash memory in 55-nm CMOS [J]. IEEE Trans Elec Dev, 2020, 67(4): 1586-1592.
[15] XU X, LIANG H, HUANG Z, et al. A highly reliable butterfly PUF in SRAM-based FPGAs [J]. IEICE Elec Expr, 2017, 14(14): 20170551.
[16] ADDABBO T, FORT A, MARCO M D, et al. Physically unclonable functions derived from cellular neural networks [J]. IEEE Trans Circ Syst I: Regul Papers, 2013, 60(12): 3205-3214.
[17] VALTCHANOV B, AUBERT A, BERNARD F, et al. Modeling and observing the jitter in ring oscillators implemented in FPGAs [C] // DDECS. Bratislava, Slovakia. 2008: 1-6.
[18] LIANG Y, WU E, CHEN X, et al. Low-timing-jitter single-photon detection using 1-GHz sinusoidally gated InGaAs/InP avalanche photodiode [J]. IEEE PhotonTech Lett, 2011, 23(13): 887-889.
[19] LIU D, LIU Z, LI L, et al. A low-cost low-power ring oscillator-based truly random number generator for encryption on smart cards [J]. IEEE Trans Circ Syst I: Regul Papers, 2016, 63(6): 608-612.
[20] PRADA-DELGADO M A, MARTíNEZ-GóMEZ C, BATURONE I. Auto-calibrated ring oscillator TRNG based on jitter accumulation [C] // ISCAS. Seville, Spain. 2020: 1-4.
[22] WANG X, LIANG H, WANG Y, et al. High-throughput portable true random number generator based on jitter-latch structure [J]. IEEE Trans Circ Syst I: Regul Paper, 2021, 68(2): 741-750.
[23] BUCHOVECKá S, LóRENCZ R, KODYTEK F, et al. True random number generator based on ROPUF circuit [C] // DSD. Limassol, Cyprus. 2016: 519-523.