[1] ZHANG S, YANG F, YAN C, et al. An efficient batch constrained bayesian optimization approach for analog circuit synthesis via multi-objective acquisition ensemble［J］. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, 41(1): 1-14.
[2] FAYAZI M, COLTER Z, AFSHARI E, et al. Applications of artificial intelligence on the modeling and optimization for analog and mixed-signal circuits: a review ［J］. IEEE Transactions on Circuits and Systems I: Regular Papers, 2021, 68(6): 2418-2431.
[3] JIAO F, MONTANO S, FERENT C, et al. Analog circuit design knowledge mining: discovering topological similarities and uncovering design reasoning strategies ［J］. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015, 34(7): 1045-1058.
[4] HE Z, ZHANG L, LIAO P, et al. Reinforcement learning driven physical synthesis ［C］ // IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT). 2020.
[5] MALLYA S M, NEVIN J H. Design procedures for a fully differential folded-cascode CMOS operational amplifier ［J］. IEEE Journal of Solid-State Circuits, 1989, 24(6): 1737-1740.
[6] CHAN P K, NG L S, SIEK L, et al. Designing CMOS folded-cascode operational amplifier with flicker noise minimisatio ［J］. Microelectronics Journal, 2001, 32(1): 69-73.
[7] FERREIRA P M, JACK O U. A gm/ID-based noise optimization for CMOS folded-cascode operational amplifier ［J］. IEEE Transactions on Circuits & Systems II: Express Briefs, 2014, 61(10): 783-787.
[8] CANNIZZARO S O, GRASSO A D, MITA R, et al. Design procedures for three-stage CMOS OTAs with nested-Miller compensation ［J］. IEEE Transactions on Circuits & Systems I: Regular Papers, 2007, 54(5): 933-940.
[9] WU W C S, HELMS W J, KUHN J A, et al. Digital-compatible high-performance operational amplifier with rail-to-rail input and output ranges ［J］. IEEE Journal of Solid-State Circuits, 2002, 29(1): 63-66.
[10] RUIZ-AMAYA J, FERNANDEZ-BOOTELLO J F, DELGADO-RESTITUTO M. Design procedure for optimizing the power consumption of two-stage Miller compensated amplifiers in SC circuits ［C］ // IEEE European Conference on Circuit Theory & Design. 2007.
[11] PALMISANO G, PALUMBO G, PENNISI S. Design procedure for two-stage CMOS transconductance operational amplifiers: a tutorial ［J］. Analog Integrated Circuits & Signal Processing, 2001, 27(3): 179-189.
[12] MAHATTANAKUL J, CHUTICHATUPORN J. Design procedure for two-stage CMOS opamp with flexible noise-power balancing scheme ［J］. IEEE Transactions on Circuits & Systems I: Regular Papers, 2005, 52(8): 1508-1514.
[13] SU L, QIU Y L. Design of a fully differential gain-boosted folded-cascode op amp with settling performance optimization ［C］ // IEEE Conference on Electron Devices & Solid-state Circuits. 2006.
[14] BAKO N, BUTKOVI Z, BARI A. Design of fully differential folded cascode operational amplifier by the gm/ID methodology ［C］ // The 33rd International Convention. MIPRO. Opatija, Croatia. 2010: 89-94.
[15] WEN B, ZHANG Q, ZHAO X, et al. Trade-offs among power consumption and other design parameters of two-stage recycling folded cascode OTA that using embedded cascode current buffer compensation technology ［J］. Integration: The VLSI Journal, 2019, 68(9): 62-70.
[16] LYU W, XUE P, YANG F, et al. An efficient bayesian optimization approach for automated optimization of analog circuits ［J］. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(6):1-14.
[17] MALLICK S, KAR R, MANDAL D, et al. Optimal sizing of CMOS analog circuits using gravitational search algorithm with particle swarm optimization ［J］. International Journal of Machine Learning & Cybernetics, 2017, 8(1): 309-331.
