With the continuous evolution of manufacturing process and the continuous increase of circuit scale, integrated circuits have gradually entered the post-Moore era. How to accurately and quickly extract parasitic capacitance parameters becomes more and more important to ensure design quality, reduce cost and shorten design cycle. In this paper, a two-dimensional capacitance extraction technology based on the segmented reservation method is proposed. The technique was based on an improved finite difference method, which used non-uniform meshing and solved asymmetric coefficient matrix equations to simulate the cross-section of interconnect structures. The proposed method could efficiently calculate the total capacitance per unit length of the main conductor and the coupling sum capacitance per unit length between the main conductor and adjacent conductors. A series of verification experiments had been completed. The experimental results show that the proposed two-dimensional capacitance extraction technology for interconnects can improve the calculation accuracy of parasitic capacitance by an average of 140 times and shorten the running time by an average of 10 %.