A wide-band low jitter phase-locked loop applied to HDMI receiver circuit was designed in a 110 nm CMOS technology. The circuit used an improved charge pump with double loop structure to realize fast locking in a wide input frequency range of 25 ~ 250 MHz, and a clock signal with a tuning range of 125 MHz~ 1.25 GHz was generated through a pseudo differential ring oscillator with high phase noise performance. The simulation results show that the locking time of the PLL is less than 1.2 μs. When the operating frequency of the oscillator is 0.8 GHz, the phase noise is -100.0 dBc/Hz @ 1 MHz, and the peak to peak jitter of the output clock is 4.49 ps.