• Chinese Journal of Quantum Electronics
  • Vol. 41, Issue 6, 881 (2024)
YUAN Lichao1,2,3,*, TAN Fengfu1,3, HUANG Zhigang1,3, CHENG Yilun1,2,3, and HOU Zaihong1,3
Author Affiliations
  • 1Key Laboratory of Atmospheric Optics, Anhui Institute of Optics and Fine Mechanics, HFIPS,Chinese Academy of Sciences, Hefei 230031, China
  • 2University of Science and Technology of China, Hefei 230026, China
  • 3Advanced Laser Technology Laboratory of Anhui Province, Hefei 230037, China
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    DOI: 10.3969/j.issn.1007-5461.2024.06.005 Cite this Article
    Lichao YUAN, Fengfu TAN, Zhigang HUANG, Yilun CHENG, Zaihong HOU. Reliability design of detector array target circuit system[J]. Chinese Journal of Quantum Electronics, 2024, 41(6): 881 Copy Citation Text show less
    Block diagram of the circuit system structure
    Fig. 1. Block diagram of the circuit system structure
    Logical block diagram of parallel redundancy reliability
    Fig. 2. Logical block diagram of parallel redundancy reliability
    Logical block diagram of reliability after redundancy
    Fig. 3. Logical block diagram of reliability after redundancy
    Reliability logic block diagram after redundant design of the circuit system
    Fig. 4. Reliability logic block diagram after redundant design of the circuit system
    CategoryImpact and consequence of failure
    Ⅰ(Catastrophic)Catastrophic failure that leads to the destruction of missile, satellite, rocket, spacecraft, or casualty
    Ⅱ(Lethal)Critical failure that results in a critical loss of system functionality and task failure
    Ⅲ(Critical)Critical failure that results in a mild loss of system functionality and task delay
    Ⅳ(Minor)Minor failure that is not sufficient to cause loss of system functionality, but results in reduced system performance andrequires unplanned repairs
    Table 1. Severity classification
    GradeDefinitionProbability of failure
    AOften happenThe probability of a module failure is greater than 20% of the total failure probability of the array target circuit system
    BSometimes happenThe probability of a module failure is greater than 10% and less than 20% of the total failure probability of the array target circuit
    COccasionally happenThe probability of a module failure is greater than 1% and less than 10% of the total failure probability of the array target circuit
    DRarely happenThe probability of a module failure is greater than 0.1% and less than 1% of the total failure probability of the array target circuit
    EVery rarely happenThe probability of a module failure is less than 0.1% of the total failure probability of the array target circuit
    Table 2. Table of fault occurrence level
    Name of the failurePrimary failure modeImpact of failureSeverityclassificationProbability level of failure
    Failure of the acquisition channel modulePhotodetector failure, amplifier failure, resistance and capacitor failureThe corresponding acquisition channel has no output or outputdistortionA
    Failure of the first-level channel selection moduleFirst-level channel selection switch failure, resistance and capacitor failureThe corresponding acquisition channel has no output or outputdistortionC
    Failure of the second-level channel selection moduleSecond-level channel selection switch failure, resistance and capacitor failureThe corresponding acquisition channel has no output or outputdistortionD
    Failure of the main control moduleDevice failure such as FPGA and AD converterThe system does not work properly and the task failsC
    Failure of the power supply moduleDevice failure such as filter and regulatorThe system does not work properly and the task failsC
    Failure of the interface moduleLVDS driver, RS-422 driver and other device failureThe system does not work properly and the task failsB
    Table 3. Array target circuit system module failure analysis table
    Module nameImportance
    Acquisition channel module0.002
    First-level channel selection module0.033
    Second-level channel selection module0.500
    Main control module1.000
    Power supply module1.000
    Interface module1.000
    Table 4. Importance of each module
    Module nameComplexity
    Acquisition channel module0.8787
    First-level channel selection module0.0982
    Second-level channel selection module0.0064
    Main control module0.0102
    Power supply module0.0034
    Interface module0.0031
    Total1.0000
    Table 5. Complexity of each module
    The name of the failureFailure rate/h
    Failure of the acquisition channel module9.33×10-4
    Failure of the first-level channel selection module7.03×10-5
    Failure of the second-level channel selection module4.58×10-6
    Failure of the main control module1.11×10-5
    Failure of the power supply module6.49×10-6
    Failure of the interface module1.14×10-4
    Table 6. Failure rate of each module
    Module nameReliability
    Acquisition channel module0.99534586
    First-level channel selection module0.99964856
    Second-level channel selection module0.99997710
    Main control module0.99994450
    Power supply module0.99996755
    Interface module0.99943016
    Table 7. Reliability of each module
    Module nameReliability
    Acquisition channel module0.99999069
    First-level channel selection module0.99998840
    Second-level channel selection module0.99998855
    Main control module0.99994450
    Power supply module0.99996755
    Interface module0.99943016
    Table 8. Reliability with considering the importance of each module
    Module nameReliability
    Acquisition channel module0.99991213
    First-level channel selection module0.99999902
    Second-level channel selection module0.99999936
    Main control module0.99999898
    Power supply module0.99999966
    Interface module0.99999969
    Table 9. Reliability required for each module
    Module nameReliability
    Main control module0.99999999
    Power supply module0.99999999
    Interface module0.99999968
    Table 10. Reliability after redundancy without considering the importance
    Lichao YUAN, Fengfu TAN, Zhigang HUANG, Yilun CHENG, Zaihong HOU. Reliability design of detector array target circuit system[J]. Chinese Journal of Quantum Electronics, 2024, 41(6): 881
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